Functional Verification of Arithmetic Logic Unit and Instruction Fetch Unit of a 32-bit RV321M ISA based RISC-V Processor

Verma, Reshma; C S, Hrishikesh; Shrinivasan, Lakshmi

doi:10.1109/conecct62155.2024.10677337

2024 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) 2024

DOI: 10.1109/conecct62155.2024.10677337

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Functional Verification of Arithmetic Logic Unit and Instruction Fetch Unit of a 32-bit RV321M ISA based RISC-V Processor

Reshma Verma,

Hrishikesh C S,

Lakshmi Shrinivasan

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Functional Verification of Arithmetic Logic Unit and Instruction Fetch Unit of a 32-bit RV321M ISA based RISC-V Processor

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