FreePDK: An Open-Source Variation-Aware Design Kit

Stine, James E.; Castellanos, Ivan D.; Wood, Mark L.; Henson, J.; Love, F.; Davis, W. Rhett; Franzon, Paul D.; Bucher, M.; Basavarajaiah, Sunil; Oh, Julie; Jenkal, Ravi

doi:10.1109/mse.2007.44

Cited by 334 publications

(125 citation statements)

References 1 publication

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“…The radix-4 dual recoded squaring circuit and a general purpose multiplier were both implemented in verilog and mapped to OSU standard cell library [SCWH07]. Both circuits were constrained to run within a 20ns clock-edge and were implemented for 16, 32, and 64 bit-widths.…”

Section: Resultsmentioning

confidence: 99%

A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits

Moore

Thornton

Matula

2008

2008 42nd Asilomar Conference on Signals, Systems and Computers

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Abstract:We introduce an implementation of a radix 4 dual recoding procedure for the squaring operation of an n-bit number which reduces the number of bit product terms employed in the previously known squaring methods obtained by either Booth radix-4 recoded multiplication or by radix 2 squaring. Several other squaring algorithms have been developed such as [WSMB99], [YW01], and [SNC01]. Employing the dual recoded radix-4 procedure for design of a squaring circuit introduces a significant reduction in power and area. Architecturally, radix-4 dual recoded squaring uses only the 1's complement representation which allows for a simpler PPG structure as compared to the 2's complement representation required for Booth radix-4 multiplication.

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Section: Resultsmentioning

confidence: 99%

A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits

Moore

Thornton

Matula

2008

2008 42nd Asilomar Conference on Signals, Systems and Computers

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“…These architectures are implemented using static CMOS gates from the Nangate Open Cell Library (OCL, [18]), which contains 45nm technology standard cells specified by the Predictive Technology Model [19]. For dynamic CMOS DOR gates of the new hybrid fault-tolerant architecture, we use the DOR4 cell designed in [13] according to design and electrical rules of the FreePDK process design kit [20].…”

Section: Discussionmentioning

confidence: 99%

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

et al. 2014

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This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS'85 and ITC'99 benchmark circuits show that our approach has an area cost of about 3% to 6% with a power consumption saving of about 33% compared to TMR architectures. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Springer Science+Business Media New York.

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“…Three application kernels with different profiles are used to evaluate the two platform types: MJPEG video decoding from multimedia domain; Smith-Waterman (SW) algorithm used to find similar regions in DNA sequences and advanced encryption standard (AES), a worldwide used cryptography application kernel. Their evaluation follows the simulation flow illustrated in Figure 4 according to the following steps: 1) a netlist is obtained by logic synthesis of the multicore architecture using an open source design kit for 45nm CMOS technology [20], the RTL VHDL system description and block constraints to detect, e.g., glitches, slow paths and clock skew; 2) the target application and the microkernel are compiled using GCC compiler (version 4.4 or above). The output is the object code for each input file, mapped onto clusters according to Section 4.1.2; 3) the object code produced by combining the application and the microkernel is simulated with the netlist in the Cadence Incisive Simulator [21], producing performance values; 4) memory property is evaluated with NVSim tool [22], e.g.…”

Section: Setup Informationmentioning

confidence: 99%

Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures

Garibotti

Butko

Ost

et al. 2016

IEEE Trans. Comput.

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Abstract-A large portion of existing multithreaded embedded sofware has been programmed according to symmetric shared memory platforms where a monolithic memory block is shared by all cores. Such platforms accommodate popular parallel programming models such as POSIX threads and OpenMP. However with the growing number of cores in modern manycore embedded architectures, they present a bottleneck related to their centralized memory accesses. This paper proposes a solution tailored for an efficient execution of applications defined with shared-memory programming models onto on-chip distributed-memory multicore architectures. It shows how performance, area and energy consumption are significantly improved thanks to the scalability of these architectures. This is illustrated in an open-source realistic design framework, including tools from ASIC to microkernel.

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FreePDK: An Open-Source Variation-Aware Design Kit

Cited by 334 publications

References 1 publication

A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits

A low power radix-4 dual recoded integer squaring implementation for use in design of application specific arithmetic circuits

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures

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