FPGA implementation of neighborhood-of-four cellular automata random number generators

Shackleford, Barry; Tanaka, Motoo; Carter, Richard J.; Snider, Greg

doi:10.1145/503048.503064

Cited by 46 publications

(12 citation statements)

References 13 publications

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“…in [2,3,16]. Reference [3] is particularly convenient for our application because is does not require the use of an analog Phase-Locked Loop (PLL) as in [2] and is therefore applicable to a wide range of FPGAs, including Xilinx ones.…”

Section: Mask Generationmentioning

confidence: 99%

FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

Standaert

Rouvroy

Quisquater

2006

2006 International Conference on Field Programmable Logic and Applications

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This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked DES. In particular, we use the large embedded memories available in the Xilinx Virtex-II pro FPGAs to store precomputed and masked substitution tables. Compared to an unprotected DES design, our proposal only requires 45% more logic resources and 128 Kbit of memory and yields a throughput of about 1 Gbit/sec.

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Section: Mask Generationmentioning

confidence: 99%

FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

Standaert

Rouvroy

Quisquater

2006

2006 International Conference on Field Programmable Logic and Applications

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“…Due to their regular nature and relatively low prototyping costs, FPGA (Field Programmable Gate Arrays) are widely used to implement CA [10]. Recently, in [11] we presented a scalable hardware implementation in FPGA of a specific CA (the chaotic counter HCA 101).…”

Section: Introductionmentioning

confidence: 99%

Algebraic normal form for rapid prototyping of elementary hybrid cellular automata in FPGA

Dogaru

2010

2010 3rd International Symposium on Electrical and Electronics Engineering (ISEEE)

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This paper introduces a methodology based on algebraic normal form representations and software tools to rapidly generate the VHDL code description of elementary hybrid cellular automata with arbitrary parameters. Such parameters include the CA local rule, the number of cells and the mask, which is specific for hybrid CA. This tool allows rapid synthesis of various CA types, as they are required by various applications. Synthesis, post-place and route and functional simulation are given for a specific case of a random number generator to prove the functionality of our software tools. IndexTerms-cellular automata, Boolean functions, algebraic normal form, Reed-Muller codes, VHDL, FPGA.

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“…the only way to find state x iþn from x n is to step through all the The period of a given generator is also difficult to determine, as there are likely to be multiple state-cycles of different lengths, with the initial state selecting which cycle is used. One dimensional, nearest-neighbour CA generators have been used instead of LFSRs in VLSI for random bit generation [10], but the quality of simple onedimensional sequences is often poor. In [23] more complex configurations are considered, such as four input functions to take advantage of 4-LUTs, and different connection topologies. This gives higher statistical quality, but because all four LUT inputs are used there is no easy way to load or store the generator_s state without partial reconfiguration or extra LUTs.…”

Section: Introductionmentioning

confidence: 99%

High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices

Thomas

Luk

2007

J VLSI Sign Process Syst Sign Image Video Technol

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This paper presents a family of uniform random number generators designed for efficient implementation in Lookup table (LUT) based FPGA architectures. A generator with a period of 2 k j1 can be implemented using k flip-flops and k LUTs, and provides k random output bits each cycle. Each generator is based on a binary linear recurrence, with a state-transition matrix designed to make best use of all available LUT inputs in a given FPGA architecture, and to ensure that the critical path between all registers is a single LUT. This class of generator provides a higher sample rate per area than LFSR and Combined Tausworthe generators, and operates at similar or higher clock-rates. The statistical quality of the generators increases with k, and can be used to pass all common empirical tests such as Diehard, Crush and the NIST cryptographic test suite. Theoretical properties such as global equidistribution can also be calculated, and best and average case statistics shown. Due to the large number of random bits generated per cycle these generators can be used as a basis for generators with even higher statistical quality, and an example involving combination through addition is demonstrated.

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FPGA implementation of neighborhood-of-four cellular automata random number generators

Cited by 46 publications

References 13 publications

FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks

Algebraic normal form for rapid prototyping of elementary hybrid cellular automata in FPGA

High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices

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