FPGA implementation of a matrix structure for integer division

Alecsa, Bogdan; Ioan, Aleodor Daniel

doi:10.1109/iseee.2010.5628505

Cited by 5 publications

(1 citation statement)

References 7 publications

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“…FPGA (Field Programmable Gate Array) devices offer integrated elements with complexities of the application oriented integrated circuits (ASIC -Application Specific Integrated Circuit), with the advantage of programmability or better said, of configurability [5]. The FPGA devices allow the design of specialized hardware architectures with the advantage of the flexibility programmable environment that can be implemented [6]. Based on these devices, hardware supports for RTOS primitives that can be easily implemented [7] [8].…”

Section: Introductionmentioning

confidence: 99%

Improving interrupt handling in the nMPRA

Gaitan

Găitan

Moisuc

2014

2014 International Conference on Development and Application Systems (DAS)

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In the most Real Time Operating Systems (RTOS), the interrupt handlers are implemented in software and they can increase the response time to external events and the overload of the CPU. Therefore, the newest RTOSs implement in hardware the interrupt handlers in order to eliminate these two problems. By analyzing traditional models for the management of interrupts, we can emphasize their inability to provide the temporal determinism required in real-time systems. This paper presents an interrupt handler implemented in hardware based on a method that uses a unified space of priorities for the tasks and interrupts, so there is not a specialized interrupt controller. This solution is integrated in the MPRA (Multi Pipeline Register Architecture) processor that contains a hardware RTOS. The major difference compared to other architectures with hardware scheduler is that the MPRA is a multi-pipeline architecture, which means that each task has its own set of pipeline registers.

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