FPGA based implementation of low-latency floating-point exponential function

Low-Power and Low-Latency Hardware Implementation of Approximate Hyperbolic and Exponential Functions for Embedded System Applications

“…Table II compares our proposed design to different methodologies described in the literature. The proposed architecture improves latency and hardware cost, however, the technique described in [35] surpasses the proposed design in error metrics and broad range owing to its usage of floating-point with an accuracy of 55 bits, the lookup table as 16Kb BRAM, and expensive hardware. The proposed architecture and the approach described in [35] utilize different accuracy bits and number formats, with the proposed method using 16 bits and fixed-point format and [35] employing 55 bits and floatingpoint format.…”

“…The proposed architecture improves latency and hardware cost, however, the technique described in [35] surpasses the proposed design in error metrics and broad range owing to its usage of floating-point with an accuracy of 55 bits, the lookup table as 16Kb BRAM, and expensive hardware. The proposed architecture and the approach described in [35] utilize different accuracy bits and number formats, with the proposed method using 16 bits and fixed-point format and [35] employing 55 bits and floatingpoint format. Although the maximum frequency is the same for both methods, the proposed method reduced latency, LUT, and FF by 82%, 91%, and 92%, respectively, when compared to [35].…”

“…To show the superiority and highlight the advantages of our architectures for generating the exponential function known as Approximate Exponential Composited-Stair Function (ApproxCSF), compared to other best FPGA-implementing architectures. The first architecture of the exponential function is designed only for the negative range, and is compared with the architecture developed by [33], [34] the conventional Cordic algorithm described in [35] and Xilinx Cordic IP core V4. All hardware was simulated with a clock of 5 ns, but the non-pipelined proposed architecture was simulated with 10 ns.…”

“…The proposed architecture and the approach described in [35] utilize different accuracy bits and number formats, with the proposed method using 16 bits and fixed-point format and [35] employing 55 bits and floatingpoint format. Although the maximum frequency is the same for both methods, the proposed method reduced latency, LUT, and FF by 82%, 91%, and 92%, respectively, when compared to [35]. The objective of the proposed method is to minimize power consumption by relaxing the level of accuracy.…”