FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size

Toledo-Moreo, F. Javier; Martínez-Álvarez, J. Javier; Garrigós-Guerrero, J.; Vicente, José Manuel Ferrández

doi:10.1016/j.sysarc.2012.06.002

Cited by 21 publications

(17 citation statements)

References 24 publications

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“…For substitute algorithms that improve the efficiency of convolution kernel modules [4][5][6][7], the computational complexity and hardware consumption will shrink in proportion with the number of MSAs by applying a recurrent decomposition. Thus, these schemes can benefit from RD architectures.…”

Section: Discussionmentioning

confidence: 99%

“…Note that the benefits apply to all MSAs types (e.g. SA [4], LUT [5], and log 2 and inverse-log 2 approximations [6]), as their computational complexities all reduce proportionally with the number of MSAs.…”

Section: A Fpga Implementationmentioning

confidence: 99%

“…These schemes sacrifices processing speed in order to reduce hardware consumption. A second category of methods replaces the multipliers with alternatives, such as shift-and-accumulation (SA) operations [4], look up table (LUT) [5], and log 2 and inverse-log 2 approximations [6]. However, the total number of multiplications or substitute algorithms (MSAs) remains untouched in these multiplier-less implementations.…”

Section: Introductionmentioning

confidence: 99%

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Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Yang

Bharath

2016

IEEE Trans. Circuits Syst. II

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Abstract-Two-dimensional (2-D) convolution is a widely used operation in image processing and computer vision, characterized by intensive computation and frequent memory accesses. Previous efforts to improve the performance of field-programmable gate array (FPGA) convolvers focused on the design of buffering schemes and on minimizing the use of multipliers. A recently proposed recurrently decomposable (RD) filter design method can reduce the computational complexity of 2-D convolutions by splitting the convolution between an image and a large mask into a sequence of convolutions using several smaller masks. This brief explores how to efficiently implement RD based 2-D convolvers using FPGA. Three FPGA architectures are proposed based on RD filters, each with a different buffering scheme. The conclusion is that RD based architectures achieve higher area efficiency than other previously reported state-of-the-art methods, especially for larger convolution masks. An area efficiency metric is also suggested, which allows the most appropriate architecture to be selected.Index Terms-Field-programmable gate arrays (FPGAs), large convolution mask, recurrently decomposable, two-dimensional (2-D) convolution.

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Section: Discussionmentioning

confidence: 99%

Section: A Fpga Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Yang

Bharath

2016

IEEE Trans. Circuits Syst. II

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“…[4–8]. The filtering operation can be performed either in spatial domain or frequency domain however since the images are inherently encoded in spatial domain therefore the spatial domain filtering is preferred [9, 10]. In spatial domain, the filtering operation is carried out by convolving the filter mask with neighborhood pixels of input image [11].…”

Section: Introductionmentioning

confidence: 99%

“…This coefficient approximation may adversely effects the accuracy of filtered outputs. The second approach is based on reducing the total count of multipliers required by the filter design by reducing effective coefficients count without any change in its value therefore accurately calculates filtered outputs [9, 15–19]. …”

Section: Introductionmentioning

confidence: 99%

A Low Cost Structurally Optimized Design for Diverse Filter Types

et al. 2016

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A wide range of image processing applications deploys two dimensional (2D)-filters for performing diversified tasks such as image enhancement, edge detection, noise suppression, multi scale decomposition and compression etc. All of these tasks require multiple type of 2D-filters simultaneously to acquire the desired results. The resource hungry conventional approach is not a viable option for implementing these computationally intensive 2D-filters especially in a resource constraint environment. Thus it calls for optimized solutions. Mostly the optimization of these filters are based on exploiting structural properties. A common shortcoming of all previously reported optimized approaches is their restricted applicability only for a specific filter type. These narrow scoped solutions completely disregard the versatility attribute of advanced image processing applications and in turn offset their effectiveness while implementing a complete application. This paper presents an efficient framework which exploits the structural properties of 2D-filters for effectually reducing its computational cost along with an added advantage of versatility for supporting diverse filter types. A composite symmetric filter structure is introduced which exploits the identities of quadrant and circular T-symmetries in two distinct filter regions simultaneously. These T-symmetries effectually reduce the number of filter coefficients and consequently its multipliers count. The proposed framework at the same time empowers this composite filter structure with additional capabilities of realizing all of its Ψ-symmetry based subtypes and also its special asymmetric filters case. The two-fold optimized framework thus reduces filter computational cost up to 75% as compared to the conventional approach as well as its versatility attribute not only supports diverse filter types but also offers further cost reduction via resource sharing for sequential implementation of diversified image processing applications especially in a constraint environment.

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A Review of Image Interest Point Detectors: From Algorithms to FPGA Hardware Implementations

Torres-Huitzil

2016

Image Feature Detectors and Descriptors

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FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size

Cited by 21 publications

References 24 publications

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

A Low Cost Structurally Optimized Design for Diverse Filter Types

A Review of Image Interest Point Detectors: From Algorithms to FPGA Hardware Implementations

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