FPGA-based Acceleration for Convolutional
Neural Networks on PYNQ-Z2

Huynh, Thang Viet

doi:10.12785/ijcds/110136

Cited by 12 publications

(5 citation statements)

References 14 publications

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“…Refs. [33][34][35][36] have deployed various neural networks and achieved impressive optimization results.…”

Section: Model Deployment On Fpga Development Boardmentioning

confidence: 99%

TensorRT Powered Model for Ultra-Fast Li-Ion Battery Capacity Prediction on Embedded Devices

Zhu,

Qian,

Gao

2024

Energies

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The LSTM neural network is often employed for time-series data prediction due to its strong nonlinear mapping capability and memory effect, allowing for better identification of complex data characteristics. However, the large computational workload required by neural networks can result in longer prediction times, making deployment on time-sensitive embedded devices challenging. To address this, TensorRT, a software development kit for NVIDIA hardware platforms, offers optimized network structures and reduced inference times for deep learning inference applications. Though TensorRT inference is GPU-based like other deep learning frameworks, TensorRT outperforms comparable frameworks in terms of inference speed. In this paper, we compare the inference time consumption and prediction deviation of various approaches on CPU, GPU, and TensorRT, while also exploring the effects of different quantization approaches. Our experiments demonstrate the accuracy and inference latency of the same model on the FPGA development board PYNQ-Z1 as well, though the best results were obtained using NVIDIA Jetson Xavier NX. The results show an approximately 50× improvement in inference speed compared to our previous technique, with only a 0.2% increase in Mean Absolute Percentage Error (MAPE). These works highlight the effectiveness and efficiency of TensorRT in reducing inference times, making it an excellent choice for time-sensitive embedded device deployments that require high precision and low latency.

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“…Refs. [33][34][35][36] have deployed various neural networks and achieved impressive optimization results.…”

Section: Model Deployment On Fpga Development Boardmentioning

confidence: 99%

TensorRT Powered Model for Ultra-Fast Li-Ion Battery Capacity Prediction on Embedded Devices

Zhu,

Qian,

Gao

2024

Energies

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“…A co-design framework for hardware and software targeting ML applications on the PYNQ-Z2 board has been developed [35].…”

Section: Deep Learning Implementation On Fpga-based Acceleratorsmentioning

confidence: 99%

AI-Driven Pheno-Parenting: A Deep Learning Based Plant Phenotyping Trait Analysis Model on a Novel Soilless Farming Dataset

Hati

Singh

2023

IEEE Access

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Agriculture 4.0 will be data-driven and utilize modern technology in order to monitor plant life cycles and traits resulting in better yield. Pheno-parenting, a new concept derives certain methodologies adopted in plant phenotyping which monitors plants at various stages of their life cycle and supports their growth by deploying modern tools and technologies. In this work, a small-scale Hydroponic system was set up for plant life cycle image data collection and analysis, which consists of thirty plants of three species (i.e., Petunia, Pansy, Calendula) with ten plants from each species grown. A Deep Neural Network (DNN) based approach has been adopted to analyse the key tasks such as plant species recognition, growth analysis, health analysis, and yield stage identification. Calendula plants have been correctly recognised with above 95% detection accuracy in all test cases The result thus obtained indicates, side-view images are more effective at identifying species and tracking growth. On the other hand, top-view photographs do a better job of capturing the texture and colour characteristics of leaves and budding flowers. The Growth Development Index (GDI) metric, which first rises with an increase in nutrient input up to 31 ml and then saturates, has been proposed to provide a better understanding of plant growth, health, and productivity.

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“…Machine learning research and prototyping have made extensive use of it. For instance, authors in [207] used this board for implementing CNNs. Xilinx's configurable DPU IP [7] can also be used together with PYNQ board for creating a network with the desired number of layers, activation functions etc.. Vivado [22], Vitis [21] and Python can be used to work with PYNQ board.…”

Section: Embedded Ai Acceleratorsmentioning

confidence: 99%

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

et al. 2022

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In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is a way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed. This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.INDEX TERMS Machine learning, field programmable gate array (FPGA), deep neural networks (DNN), deep learning (DL), application specific integrated circuits (ASIC), artificial intelligence (AI), central processing unit (CPU), graphics processing unit (GPU), hardware accelerators. FIGURE 3. A single ANN neuron with its elements (inputs, weights, bias, summer, activation function, and output).

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FPGA-based Acceleration for Convolutional Neural Networks on PYNQ-Z2

Cited by 12 publications

References 14 publications

TensorRT Powered Model for Ultra-Fast Li-Ion Battery Capacity Prediction on Embedded Devices

TensorRT Powered Model for Ultra-Fast Li-Ion Battery Capacity Prediction on Embedded Devices

AI-Driven Pheno-Parenting: A Deep Learning Based Plant Phenotyping Trait Analysis Model on a Novel Soilless Farming Dataset

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

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