FPGA and SoC Devices Applied to New Trends in Image/Video and Signal Processing Fields

Bravo-Muñoz, Ignacio; Galilea, José Luis Lázaro; Gardel, Alfredo

doi:10.3390/electronics6020025

Cited by 7 publications

(10 citation statements)

References 6 publications

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“…The MT-type division-less algorithm, as shown in Equations (14) and (15), can be described graphically by the block scheme in Figure 4. Obviously, the inputs in the algorithm are the sampled encoder position x kand the elapsed time intervalsince the recent encoder pulse, i.e., δt k , whereas the main output of the algorithm is the estimated velocityv k .…”

Section: The Mt-type Division-less Algorithm Of the Second Ordermentioning

confidence: 99%

“…x x x , and ˆk v is the value of estimated average velocity in the k-th sampling period. The MT-type division-less algorithm, as shown in Equations (14) and (15), can be described graphically by the block scheme in Figure 4. Obviously, the inputs in the algorithm are the sampled encoder position k…”

Section: The Mt-type Division-less Algorithm Of the Second Ordermentioning

confidence: 99%

“…They offer possibilities for integrating complex hardware systems and their interfaces into a single FPGA chip. FPGA devices have reached a high maturity level in terms of performance, power consumption, and cost, which makes them suitable for different application fields [2] that involve sensor systems [3,4], control systems [5,6], haptic interfaces [7,8], robotics [9][10][11], and other advanced electronic devices for signal processing and communications, e.g., [12][13][14][15]. They can also be useful for advanced velocity estimation methods, since they can easily be designed for custom signal conditioning and provide fast dedicated digital logic [16].…”

Section: Introductionmentioning

confidence: 99%

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The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

Hace

2019

Electronics

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Advanced motion control applications require smooth and highly accurate high-bandwidth velocity feedback, which is usually provided by an incremental encoder. Furthermore, high sampling rates are also demanded in order to achieve cutting-edge system performance. Such control system performance with high accuracy can be achieved easily by FPGA-based controllers. On the other hand, the well-known MT method for velocity estimation has been well proven in practice. However, its complexity, which is related to the inherent arithmetic division involved in the calculus part of the method, prevents its holistic implementation as a single-chip solution on small-size low-cost FPGAs that are suitable for practical optimized control systems. In order to overcome this obstacle, we proposed a division-less MT-type algorithm that consumes only minimal FPGA resources, which makes it proper for modern cost-optimized FPGAs. In this paper, we present new results. The recursive discrete algorithm has been further optimized, in order to improve the accuracy of the velocity estimation. The novel algorithm has also been implemented on the experimental FPGA board, and validated by practical experiments. The enhanced algorithm design resulted in improved practical performance.

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Section: The Mt-type Division-less Algorithm Of the Second Ordermentioning

confidence: 99%

Section: The Mt-type Division-less Algorithm Of the Second Ordermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

Hace

2019

Electronics

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“…The limitations are unsuitable for some real-time system applications. Nowadays, the hardware implementation of image algorithms has been widely applied in the field of image processing with the advantages of high degree of parallelism, integration and resulting high speed, low power consumption, and low cost [14,15]. The implementation of image algorithms through hardware can overcome the computational bottleneck and improve the processing speed of the system.…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation for an Improved Full-Pixel Search Algorithm Based on Normalized Cross Correlation Method

et al. 2018

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Digital speckle correlation method is widely used in the areas of three-dimensional deformation and morphology measurement. It has the advantages of non-contact, high precision, and strong stability. However, it is very complex to be carried out with low speed software implementation. Here, an improved full pixel search algorithm based on the normalized cross correlation (NCC) method considering hardware implementation is proposed. According to the field programmable gate array (FPGA) simulation results, the speed of hardware design proposed in this paper is 2000 faster than that of software in single point matching, and 600 times faster than software in multi-point matching. The speed of the presented algorithm shows an increasing trend with the increase of the template size when performing multipoint matching.

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“…Additionally, PLL has wide applications in cellular networks for carrier synchronization, especially the D2D communications which support the cellular networks [12,13]. In addition, the phase-locked loop is extensively applicable in image/video and signal processing fields for accurate signal synchronization [14]. Furthermore, the PLL also has a find application in real-time motion detection for automated video surveillance systems [15].…”

Section: Introductionmentioning

confidence: 99%

New Nonlinear Second-Order Phase-Locked Loop with Adaptive Bandwidth Regulation

2018

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Synchronization of large acquisition bandwidth brings great challenges to the traditional second-order phase-locked loop (PLL). To address the contradiction between acquisition bandwidth and noise suppression capability of the traditional PLL, a new second-order PLL coupled with a nonlinear element is proposed. The proposed nonlinear second-order PLL regulates the loop noise bandwidth adaptively by the nonlinear module. When a large input–output phase error occurs, this PLL reduces the frequency offset quickly by taking advantage of the large bandwidth. When the phase error is reduced by the loop control, the proposed PLL suppresses noises by using the small bandwidth to increase the tracking accuracy. Simulation results demonstrate that the tracking speed of the proposed PLL is increased considerably, and its acquisition bandwidth is increased to 18.8 kHz compared with that of the traditional second-order PLL (4 kHz).

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FPGA and SoC Devices Applied to New Trends in Image/Video and Signal Processing Fields

Abstract: Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in different areas and fields for the past 20 years. [...]

Cited by 7 publications

References 6 publications

The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

Hardware Implementation for an Improved Full-Pixel Search Algorithm Based on Normalized Cross Correlation Method

New Nonlinear Second-Order Phase-Locked Loop with Adaptive Bandwidth Regulation

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