Formation of parallel (111) twin boundaries in silicon growth from the melt explained by molecular dynamics simulations

Pohl, Johan; Müller, Michael; Seidl, A.; Albe, Karsten

doi:10.1016/j.jcrysgro.2009.09.043

Cited by 42 publications

(24 citation statements)

References 25 publications

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“…Molecular dynamics simulations by Pohl, et al, 26 of dendritic silicon crystal growth showed that twins typically need to nucleate at either grain boundaries or at the three-phase boundary of the melt-crystal-ambient system. Such sites in the present system could be provided by silicon growth at the surfaces of silicide grains.…”

confidence: 99%

Titanium catalyzed silicon nanowires and nanoplatelets

et al. 2013

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Silicon nanowires, nanoplatelets, and other morphologies resulted from silicon growth catalyzed by thin titanium layers. The nanowires have diameters down to 5 nm and lengths to tens of micrometers. The two-dimensional platelets, in some instances with filigreed, snow flake-like shapes, had thicknesses down to the 10 nm scale and spans to several micrometers. These platelets grew in a narrow temperature range around 900 celsius, apparently representing a new silicon crystallite morphology at this length scale. We surmise that the platelets grow with a faceted dendritic mechanism known for larger crystals nucleated by titanium silicide catalyst islands

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confidence: 99%

Titanium catalyzed silicon nanowires and nanoplatelets

et al. 2013

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“…To control the morphology of the crystal-melt interface during unidirectional growth processes is crucial to obtaining highquality crystals because it affects the macro-and microstructures and eventually the mechanical, optical, and electrical properties of materials. It has been suggested that the generation of crystal defects, such as dislocations and twin boundaries, is related to the morphology of the crystal-melt interface [12][13][14]. The segregation of impurities is also dependent on the interfacial morphology [15].…”

Section: Crystal-melt Interface During Unidirectional Growthmentioning

confidence: 99%

“…It has also been reported that parallel twins can form at (111) microfacets at a crystal-melt interface [43]. Pohl et al studied this issue by classical molecular dynamics simulation [13]. In their simulations, parallel twin formation at the normal grain boundary was observed, but that at microfacets on a crystal-melt interface was not observed.…”

Section: Parallel-twin Formationmentioning

confidence: 99%

Crystal Growth Behaviors of Silicon during Melt Growth Processes

Fujiwara

2012

International Journal of Photoenergy

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It is imperative to improve the crystal quality of Si multicrystal ingots grown by casting because they are widely used for solar cells in the present and will probably expand their use in the future. Fine control of macro- and microstructures, grain size, grain orientation, grain boundaries, dislocation/subgrain boundaries, and impurities, in a Si multicrystal ingot, is therefore necessary. Understanding crystal growth mechanisms in melt growth processes is thus crucial for developing a good technology for producing high-quality Si multicrystal ingots for solar cells. In this review, crystal growth mechanisms involving the morphological transformation of the crystal-melt interface, grain boundary formation, parallel-twin formation, and faceted dendrite growth are discussed on the basis of the experimental results of in situ observations.

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“…The {111} lattice planes in the diamond structure of Si and zinc-blende CdTe, ZnO, ZnS correspond to {112} lattice planes in kesterite-type Cu 2 ZnSnSe 4 and Cu 2 ZnSnS 4 , and chalcopyrite-type Cu(In,Ga)S 2 , Cu(In,Ga)Se 2 (CIGS) and CuInSe 2 (CIS). Stacking faults of these planes can easily form during film growth due to low stacking fault energies [1,2,3,4,5]. Moreover, stacking faults may cause barriers for majority charge carriers by forming buried wurtzite structures [6,7].…”

Section: Introductionmentioning

confidence: 99%

“…(b) Diffractogram of the same sample after annealing to 550°C. (c) Schematic of the grain growth model: a combination of grain size and stacking fault density is decisive for which grains grow(1,2,3) at the expense of others(4,5…”

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confidence: 99%

Stacking fault reduction during annealing in Cu-poor CuInSe2 thin film solar cell absorbers analyzed by in situ XRD and grain growth modeling

Stange

Brunken

Greiner

et al. 2019

Journal of Applied Physics

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Buried wurtzite structures composed by stacking faults of the {111} planes in zinc-blende and {112} planes in chalcopyrite structures can result in barriers for charge carrier transport. A precise understanding of stacking fault annihilation mechanisms is therefore crucial for the development of effective deposition processes. During co-evaporation of Cu(In,Ga)Se 2a photovoltaic absorber material showing record efficiencies of up to 22.9 % for thin film solar cellsa reduction of stacking faults occurs at the transition from a Cu-poor to a Cu-rich film composition, parallel to grain growth, which is suggesting that the two phenomena are coupled. Here, we show by in-situ synchrotron X-ray diffraction during annealing of Cu-poor CuInSe 2 thin films, that stacking faults can be strongly reduced through annealing, without passing through a Cu-rich film composition. We simulate the evolution of the XRD stacking fault signal with a simple numerical model of grain growth driven by stacking fault energy and grain boundary curvature. The results support the hypothesis that the stacking fault reduction can be explained by grain growth. The model is used to make predictions on annealing times and temperatures required for stacking fault reduction and could be adapted for polycrystalline thin films with similar morphology.

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Formation of parallel (111) twin boundaries in silicon growth from the melt explained by molecular dynamics simulations

Cited by 42 publications

References 25 publications

Titanium catalyzed silicon nanowires and nanoplatelets

Titanium catalyzed silicon nanowires and nanoplatelets

Crystal Growth Behaviors of Silicon during Melt Growth Processes

Stacking fault reduction during annealing in Cu-poor CuInSe2 thin film solar cell absorbers analyzed by in situ XRD and grain growth modeling

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