Fluorocarbon assisted atomic layer etching of SiO2 using cyclic Ar/C4F8 plasma

126

106

Current trends in semiconductor device manufacturing impose extremely stringent requirements on nanoscale processing techniques, both in terms of accurately controlling material properties and in terms of precisely controlling nanometer dimensions. To take nanostructuring by dry etching to the next level, there is a fast growing interest in so-called atomic layer etching processes, which are considered the etching counterpart of atomic layer deposition processes. In this article, past research efforts are reviewed and the key defining characteristics of atomic layer etching are identified, such as cyclic step-wise processing, self-limiting surface chemistry, and repeated removal of atomic layers (not necessarily a full monolayer) of the material. Subsequently, further parallels are drawn with the more mature and mainstream technology of atomic layer deposition from which lessons and concepts are extracted that can be beneficial for advancing the field of atomic layer etching.

Section: The Early Days Of Atomic Layer Etchingmentioning

confidence: 99%

Atomic Layer Etching: What Can We Learn from Atomic Layer Deposition?

Faraz

Roozeboom

Knoops

et al. 2015

126

106

“…as seen in the case of SiO 2 ALE. 9,95,99 Additionally, the somewhat relaxed expectations relative to true atomistic level control make the prospect of broad implementation more realistic.…”

Section: Issues and Needsmentioning

confidence: 99%

“…Example of thickness evolution during eight cycles of an SiO 2 ALE process. 99 which enables controlled removal of Angstrom-thick SiO 2 layers per cycle.…”

Section: Iii-v: Gaasmentioning

confidence: 99%

Atomic Layer Etching at the Tipping Point: An Overview

Oehrlein

Metzler

2015

225

162

The ability to achieve near-atomic precision in etching different materials when transferring lithographically defined templates is a requirement of increasing importance for nanoscale structure fabrication in the semiconductor and related industries. The use of ultra-thin gate dielectrics, ultra thin channels, and sub-20 nm film thicknesses in field effect transistors and other devices requires near-atomic scale etching control and selectivity. There is an emerging consensus that as critical dimensions approach the sub-10 nm scale, the need for an etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), has become essential, and that the more than 30-year quest to complement/replace continuous directional plasma etching (PE) methods for critical applications by a sequence of individual, self-limited surface reaction steps has reached a crucial stage. A key advantage of this approach relative to continuous PE is that it enables optimization of the individual steps with regard to reactant adsorption, self-limited etching, selectivity relative to other materials, and damage of critical surface layers. In this overview we present basic approaches to ALE of materials, discuss similarities/crucial differences relative to thermal and plasma-enhanced ALD, and then review selected results on ALE of materials aimed at pattern transfer. The overview concludes with a discussion of opportunities and challenges ahead. A requirement of increasing importance for nanoscale device fabrication is the ability to achieve atomic scale etching control and materials selectivity during pattern transfer.1-8 An etching method corresponding to Atomic Layer Deposition (ALD), i.e. Atomic Layer Etching (ALE), is expected to satisfy these needs as critical dimensions continue to shrink below the 10 nm scale.Demonstrations of self-limited dry etching methods capable of near-atomic resolution have a long history in the dry etching community and a brief review will be presented below. Key challenges for these approaches have been specialized equipment, long process times and low throughput.9,10 However, a recent demonstration using a commercial plasma etch tool 10 and activities within the dry etching community 11 provide indications that the situation has changed, and that we may have reached for ALE the Tipping Point which Gladwell defined as the "the moment of critical mass, the threshold, the boiling point" when "ideas and products and messages and behaviors spread like viruses do".12 This is due to several factors, including unprecedented demands on dry etching technology introduced by the semiconductor device evolution according to Moore's law that can be satisfied by atomic layer etching, advanced capabilities in plasma etch, and the existence of a critical level of information on plasma etch and ALD methods as applied in the semiconductor fabrication space.In this article we will provide a review of background of these approaches, and focus on issues that have to be overcome for widespread implement...

“…55 We conclude that today the potential of ALD-assisted nanomanufacturing technologies like Atomic Layer Etching (ALEt) concepts derived from etch-purge-passivation/deposition-purge subroutines in (D)RIE and ALD is now clearly being recognized and promoted. 10,54,56,[57][58][59] The ongoing scaling of Moore's Law will soon require the implemention of these complementary technologies to meet the 10-nm challenges in surface and sidewall passivation of resist and feature patterns that is required to minimize interface, line edge and fin wall roughness.…”

Section: Concluding Remarks and Outlookmentioning

confidence: 99%

Cyclic Etch/Passivation-Deposition as an All-Spatial Concept toward High-Rate Room Temperature Atomic Layer Etching

Roozeboom

Bruele

Creyghton

et al. 2015

Conventional (3D) etching in silicon is often based on the 'Bosch' plasma etch with alternating half-cycles of a directional Sietch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing 'curtains' that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al 2 O 3 , SiO 2 , etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-endof-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). Today, the continuous doubling of the transistor count on planar microprocessor and memory chips in a two-year cadence has reached the point where Moore's Law (essentially an economic law) and Dennard's scaling (transistor and pitch dimensions) have approached their limits in 2D-scaling. The end of the planar device era was marked with the introduction in 2011 of the 22-nm Tri-Gate device.1,2 Figure 1 shows its design with gates surrounding the channel on three sides of vertical fins to improve gate delay.Today, at the emergence of the 10-nm technology node and the 50 th anniversary of Moore's Law, 3D device and integration solutions are being rapidly introduced both intra-chip, e.g., Gate-All-Around, 3 vertical NAND, 4 and inter-chip, e.g., 3D Through-Silicon Vias (TSVs). 5History of 3D etching.-Whereas the transistor design has been planar for most of its history, its periphery has been subjected to 3D design early on. One of the earliest 3D concepts has been the basic invention of 3D TSVs, already filed in 1958 by the famous W. Shockley, 6 cf. Fig. 2. Yet, in reality 3D Through-Silicon Via (TSV) technology took decades to accelerate the now rapidly growing stacked-chips and micro-electromechanical systems (MEMS) markets by enabling their interconnection in a 3D-integrated System-in-Package (i.e. the so-called 'More than Moore' domain). Today, the mainstream industrial technology for etching of both TSV and MEMS structures is ion-assisted etching or (Deep) Reactive Ion Etching. This method has become so ...