Flexible Error Protection for Energy Efficient Reliable Architectures

Miller, Timothy N.; Surapaneni, Nagarjuna; Teodorescu, Radu

doi:10.1109/sbac-pad.2010.37

Cited by 31 publications

(5 citation statements)

References 28 publications

(35 reference statements)

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“…Some works, e.g. [35], [36], [37] have proposed multi-core architectures that exploit redundancy at different levels of abstraction to target low-energy consumption and reliability. [35] has proposed an adaptive multicore architecture that selectively adjusts pipeline-level redundancy to satisfy reliability target with low energy consumption.…”

Section: Related Workmentioning

confidence: 99%

“…[35], [36], [37] have proposed multi-core architectures that exploit redundancy at different levels of abstraction to target low-energy consumption and reliability. [35] has proposed an adaptive multicore architecture that selectively adjusts pipeline-level redundancy to satisfy reliability target with low energy consumption. [36] has proposed a customizable chip-level redundancy technique for multi-core systems that utilizes power efficient hardware fault-detection mechanisms along with forward recovery to reduce overheads in case of fault-free executions.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Salehi

Ejlali

Al-Hashimi

2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multicore systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered: i) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving, ii) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energymanagement technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29% energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Salehi

Ejlali

Al-Hashimi

2016

IEEE Trans. Parallel Distrib. Syst.

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“…If a faulty component is detected, it is replaced with a spare component [4]. Other fault tolerance approaches try to detect and correct errors in real-time, using fully-replicated shadow pipelines [5], simple in-order pipelines that check the results of a complex out-of-order pipeline [6], or specialized checkers [7]. A common application of BISR is in 2D RAMs, where spare memory units [8] or redundant row/columns [9] are implemented.…”

Section: A Related Workmentioning

confidence: 99%

Repairing a 3-D Die-Stack Using Available Programmable Logic

Nepal

Alhelaly

Dworak

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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3D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an FPGA that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a non-programmable die by replacing the defective functionality with functionality on the FPGA. In this article, we discuss what additional logic must be added to an ASIC die to allow such a bypass to occur. We then show through detailed simulation of a 2.5D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies.Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

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“…Miller et al . propose a new approach to microprocessor reliability management that achieves reliable and energy‐efficient operation by dynamically adapting the amount of error protection to the characteristics of individual chips (to account for the effects of process variation), their runtime behavior (to account for workload variability), and the desired level of error resiliency. The ability of the system to dynamically adapt allows it to operate reliably within defined targets without wasting energy on high safety margins or over‐provisioning.…”

Section: Special Issue Papersmentioning

confidence: 99%

Latest trends in computer architectures and parallel and distributed technologies

Schulze

Rebello

Moreira

2012

Concurrency and Computation

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This special issue focuses on new developments in high performance applications, as well as the latest trends in computer architecture and parallel and distributed technologies, and is based on extended, thoroughly revised papers from the 22nd International Symposium on Computer Architecture and High Performance Computing. The authors were invited to provide extended versions of their original papers, taking into account comments and suggestions raised during the peer review process and comments from the audience during the conference. • profiling divergences in graphics processing unit (GPU) applications; • runtime failure rate targeting for energy-efficient reliability in chip microprocessors; • a queuing model-based approach for the analysis of transactional memory (TM) systems;• performance analysis of a parallel linear octree finite element mesh generation scheme;• multiple threads and parallel challenges for large simulations to accelerate a general Navier-Stokes computational fluid dynamics (CFD) code on massively parallel system; • design of energy-efficient hardware TM systems; and • clock synchronization in high-end computing environments: a strategy for minimizing clock variance at runtime.

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Flexible Error Protection for Energy Efficient Reliable Architectures

Abstract: Abstract

Cited by 31 publications

References 28 publications

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Repairing a 3-D Die-Stack Using Available Programmable Logic

Latest trends in computer architectures and parallel and distributed technologies

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