Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study

Balagopal, S. Ashwin; Viraraghavan, Janakiraman

doi:10.1109/iscas45731.2020.9180925

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…N space for an ⃗ R whose MAC tracks µ M AC| ⃗ X is not feasible. A method to pick ⃗ R from the available set of weight bit-vectors( ⃗ W b ) was proposed in [49]. Nevertheless, an average of MACs from multiple weight bit-vectors tracks µ M AC| ⃗ X better than a single ⃗ W b MAC, as is demonstrated in Section VII-A.…”

Section: Input Dependent References a Tracking The Conditional Mpdf Meanmentioning

confidence: 99%

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

Sundar¹,

Viraraghavan²,

Vijayakumar³

2022

Preprint

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<p>In-Memory Computation(IMC) of Neural-Network(NN) inference is done by performing the Multiply-ACcumulate(MAC) operation in the analog domain. Parallelly digitising MAC voltages by fitting Analog to Digital Converters(ADCs) within dense memory-pitches is a fundamental challenge for IMC engines. IMC works thus far rely on clipping the MAC-PDF to reduce the dynamic range, reducing the per data-line(DL) ADC precision requirement. In this work, we show that the per-DL ADC precision can be reduced even further by focusing on quantising the input Conditioned MAC-PDF(CMPDF), which spans a sub-range in the total MAC-PDF. We demonstrate on hardware a technique to locate the CMPDF in one-shot by tracking its mean. We show that quantisation levels about the CMPDF mean can be skewed to only span the portion of CMPDF that yields positive ReLU inputs, provided MACs are implemented as complete sums. Compared to symmetrically spanning CMPDF, this requires 20% to 40% fewer references at iso-accuracy for the investigated neural network layers. Hardware measured results for Fully-Connected NN inference on MNIST yielded < 1% accuracy drop when MAC-voltages were quantised with 4 bit references about the CMPDF mean as compared to full-range 6 bit ADC sensing the MAC-voltages. MATLAB evaluation using 3.5 to 4.2 bit CMPDF quantisation for MNIST-FCNN, CIFAR-10 Resnet-20 and VGG-11 inference yielded < 1% accuracy drop as compared to full-range 6 to 7 bit MAC quantisation. </p>

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Section: Input Dependent References a Tracking The Conditional Mpdf Meanmentioning

confidence: 99%

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

Sundar¹,

Viraraghavan²,

Vijayakumar³

2022

Preprint

Self Cite

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“…This analog representation of the MAC is digitized using ADCs [7] for further processing. Several techniques have been used to digitize the MAC, such as a serial flash ADC [12], a Successive Approximation (SAR) ADC [13,14], parallel flash ADC [15] and delta-sigma ADC [16]. The aforementioned ADC architectures aim to reduce energy consumption while fitting their layout in as few BL pitches as possible.…”

Section: Introductionmentioning

confidence: 99%

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter

Vijayakumar

Viraraghavan

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Area and energy-efficient data converters are an integral part of In-Memory Compute (IMC) engines. The conventional Digital to Analog Converters (DACs) uses binary-weighted pull-up current sources with scan-flops feeding in the digital input. These bulky pull-up devices and scan-flops make it hard to integrate along-side a memory array in an area-efficient manner. Further, it is prone to error due to local variations owing to limited digital control. In this paper, we propose an area-efficient, Word-Line (WL) pitch-aligned, layout friendly In-Memory compatible DAC (IM-DAC), whose layout resembles the 8T SRAM array very closely, thus achieving memory array-like density. Simulation results show that the worst-case INL and DNL is 2.42 LSB and -0.32 LSB, respectively. We obtained a 3.4X area advantage in comparison with the conventional DAC. The highdensity layout allows for additional calibration pull-up stacks, with minimal area penalty, that reduces the standard deviation of the linearized-current to 48.76% of the corresponding value before calibration.

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Flash Based In-Memory Multiply-Accumulate Realisation: A Theoretical Study

Cited by 2 publications

References 16 publications

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

Input Conditioned Subranging and Skewed Quantisation of MACs in IMC

An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter

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