FIVR &amp;#x2014; Fully integrated voltage regulators on 4th generation Intel&amp;#x00AE; Core&amp;#x2122; SoCs

Burton, Edward A.; Schrom, G.; Paillet, F.; Douglas, Jonathan; Lambert, William J.; Radhakrishnan, Kaladhar; Hill, Michael J.

doi:10.1109/apec.2014.6803344

Cited by 225 publications

(165 citation statements)

References 3 publications

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“…To determine the amplifier gain, average ripple levels on integrated voltage regulators are used as reference. Many of the reported ripples range between 14 and 45 mV peak-to-peak [2,3,17]. In the light of this data, upper limit for the input ripple is set to 50 mV.…”

Section: Methodology and Design Specificationsmentioning

confidence: 99%

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A CMOS Ripple Detector for Voltage Regulator Testing

et al. 2016

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This paper presents an RMS based ripple sensor for testing of fully integrated voltage regulators. A DC signal which is proportional to the input ripple amplitude is generated. Final digital pass/fail signal is obtained with a clocked comparator. The sensor can detect a peak-topeak ripple voltage of up to 50 millivolts on the 1.2 V supply rail and has 220 MHz bandwidth. The sensor is designed using IBM 90 nm CMOS technology and its functionality is verified in Cadence Virtuoso simulation environment.

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Section: Methodology and Design Specificationsmentioning

confidence: 99%

“…More importantly, there is an emerging trend toward integrating voltage regulators with SOC die/packages to improve efficiency and form factor [2]. This necessitates the use of metal-insulator-metal capacitors and package inductors for signal filtering which suffer from high effective series resistances and DC resistances.…”

Section: Introductionmentioning

confidence: 99%

A CMOS Ripple Detector for Voltage Regulator Testing

et al. 2016

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“…First, it assumes per-core DVFS adaptation which is infeasible for many-core processors as it requires per-core on-chip voltage, which would incur fairly high chip area overhead [3]. Second, the runtime complexity and overhead of a Centralized approach increases considerably with core count.…”

Section: Two-tier Hierarchical Power Managementmentioning

confidence: 99%

Shared resource aware scheduling on power-constrained tiled many-core processors

Jha

Heirman²,

Falcón³

et al. 2016

Proceedings of the ACM International Conference on Computing Frontiers

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Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today's powerconstrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases. In this paper, we propose a two-tier hierarchical power management methodology to exploit per-tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior.

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“…Integrated thin-film magnetic components will enable a new set of IC applications, such as integrated voltage regulation (IVR), where all components of a switched inductor dc-dc power converter are integrated on-chip. Integrated voltage regulation allows power to be delivered to ICs at higher voltages and then be efficiently down converted on-chip, reducing I 2 R loss in the upstream power delivery network, and enabling improved power management with a larger number of independently scalable on-chip power supplies [14]- [15].…”

Section: ) Magneticsmentioning

confidence: 99%