Fine-grained DVFS using on-chip regulators

Abstract

Limit studies on Dynamic Voltage and Frequency Scaling (DVFS) provide apparently contradictory conclusions. On the one end, early limit studies report that DVFS is effective at large timescales (on the order of million(s) of cycles) with large scaling overheads (on the order of tens of microseconds), and they conclude that there is no need for small overhead DVFS at small timescales. Recent work on the other hand -motivated by the surge of on-chip voltage regulator research -explores the potential of fine-grained DVFS and reports substantial energy savings at timescales of hundreds of cycles (while assuming no scaling overhead).This paper unifies these apparently contradictory conclusions through a DVFS limit study that simultaneously explores timescale and scaling speed. We find that coarse-grained DVFS is unaffected by timescale and scaling speed, however, fine-grained DVFS may lead to substantial energy savings for memory-intensive workloads. Inspired by these insights, we subsequently propose a fine-grained microarchitecture-driven DVFS mechanism that scales down voltage and frequency upon individual off-chip memory accesses using on-chip regulators. Fine-grained DVFS reduces energy consumption by 12% on average and up to 23% over a collection of memory-intensive workloads for an aggressively clock-gated processor, while incurring an average 0.08% performance degradation (and at most 0.14%). We also demonstrate that the proposed fine-grained DVFS mechanism is orthogonal to existing coarse-grained DVFS policies, and further reduces energy by 6% on average and up to 11% for memory-intensive applications with limited performance impact (at most 0.7%).

Embracing heterogeneity with dynamic core boosting

“…We try to solve this problem by relying on the hardware capability of accelerating the subset of cores while staying in the power budget. Dynamic voltage and frequency scaling (DVFS) has been widely used for energy efficiency [1,10]. Moreover, there have been several proposals that use dual power supplies for boosting individual cores [8,24].…”

“…Dynamic voltage and frequency scaling (DVFS) is a widely used technique for dynamic per-core performance adaptation [15,10] and some AMD commercial processors support per-core DVFS [1]. However, off-chip regulator-based DVFS incurs intolerable scaling overheads (tens of microseconds) for our purpose.…”

Value and Energy Aware Adaptive Resource Allocation of Soft Real-Time Jobs on Many-Core HPC Data Centers

“…A node (server) n contains a set of homogeneous cores C n , referred to as processing elements (PEs), which communicate via an interconnect. Each core is assumed to support DVFS [24]. A platform resource manager controls access of platform resources and coordinates the execution status of jobs submitted by the users, which facilitates efficient management of resources and incoming requests.…”

“…In case of both the events 1) and 2) or any of them, the algorithm tries to perform resource allocation for the queues job(s) having non-zero values (lines 18-28). However, if event 3) is also detected at the same time, the adaptation is tried first (lines 7-17) followed by the allocation (lines [18][19][20][21][22][23][24][25][26][27][28]. This ensures that the executing jobs are given priority over the queued jobs to be allocated so that value and energy of the executing jobs can be further optimized before doing optimizations for the queued jobs.…”

XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures

“…Sanchez and Kozyrakis, for example, show that fine-grained shared-cache cache partitioning is feasible in a large-scale CMP system [36], yielding greatly improved utilization. Similarly, multiple poweroriented studies [6,15,23] show that fine-grained, per-core DVFS regulation can greatly improve a CMP's energy efficiency. Intel has recently deployed a low-cost, fully-integrated voltage regulator in Haswell [19], and other researchers are making significant advances in supporting per-core DVFS [21,38].…”