Fin bending due to stress and its simulation

Gencer, Alp H.; Tsamados, Dimitrios; Moroz, Victor

doi:10.1109/sispad.2013.6650586

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…For scaling of FinFETs, fin height is increased to increase channel width. However, suppression of pattern leaning becomes critical for further height increase [5]. Gate-all-around (GAA) FETs were proposed for beyond FinFETs because they obtain large channel width [6].…”

Section: Introductionmentioning

confidence: 99%

Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

Zhao

Iwase

Satake³

et al. 2021

IEEE J. Electron Devices Soc.

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We investigated the formation mechanism of a rounded silicon-germanium (SiGe)-etch front (rounding) in gateall-around field-effect transistor (GAA-FET) manufacturing. This rounding is created by the isotropic etching of the SiGe layer after anisotropic etching of the SiGe/Si stack, which degrades device characteristics. The etch-time dependence of the rounding amount during isotropic SiGe etching with nitrogen trifluoride plasma indicates that rounding is mainly formed in an initial stage of SiGe etching, namely, etch time less than 15 s. Cross-sectional scanning transmission electron microscopy and energy dispersive x-ray spectroscopy (STEM EDX) measurement indicated that a Ge-containing layer formed on the sidewall of SiGe/Si patterns before isotropic SiGe etching. From these results, we propose a formation model of SiGe rounding below. The Ge composition in the Ge-containing layer has a gradient due to ion-assisted Ge diffusion during anisotropic etching of the SiGe/Si stack. This gradient induces rounding during isotropic SiGe etching because the etch rate of the SiGe layer decreases as the Ge composition decreases. To validate our model, the Gecontaining layer after anisotropic etching was removed by postetch treatment and the Ge spectra on the sidewall was reduced to the detection limit of STEM EDX. As a result, the rounding amount after isotropic SiGe etching improved from 2.7 to 1.8 nm. This reduction indicates that the formation of the Ge-containing layer during anisotropic etching of the SiGe/Si stack is one of the main causes of rounding after isotropic SiGe etching.

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Section: Introductionmentioning

confidence: 99%

Formation Mechanism of Rounded SiGe-Etch Front in Isotropic SiGe Plasma Etching for Gate-All-Around FETs

Zhao

Iwase

Satake³

et al. 2021

IEEE J. Electron Devices Soc.

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“…(1)(2)(3)(4)(5) Even though fin-based structures may be superior electrically, they are less robust than planar structures mechanically, which may give rise to some unexpected failure mechanisms. (6) Prior studies indicate that mechanical stress shows a great impact on the electrical behavior. In traditional planar MOSFETs, thermal annealing is considered to expand the filler in shallow trenches and squeeze it; thus, the channel region is subjected to a compressive stress.…”

Section: Introductionmentioning

confidence: 99%

Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET

Yang

Chuang

Lai

et al. 2019

Sensors and Materials

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In this work, a contact etch stop layer (CESL) was found to cause tensile stress above the gate of FinFET devices, and the top tensile stress introduced compressive stress in the channel. With increasing active surface area (SA), a higher compressive stress was observed. The effect of compressive stress became more evident, resulting in a lower current but a higher reliability for nFinFET devices.

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