Ferroelectric Negative-Capacitance-Assisted Phase-Transition Field-Effect Transistor

Yadav, Sameer; Upadhyay, Pranshoo; Awadhiya, Bhaskar; Kondekar, P. N.

doi:10.1109/tuffc.2021.3130194

Cited by 10 publications

(4 citation statements)

References 41 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It has been established that the electrical characteristics of a device produced in this way are poor [31]. To counteract this effect, the buffer layer is placed midway between the ferroelectric layer and the silicon substrate [32][33][34][35]. Negative capacitance is a property of ferroelectric materials such as Si-doped HfO 2 that acts like a stepup transformer and increases the device's driving current and SS [36].…”

Section: Device Architecture and Simulation Deckmentioning

confidence: 99%

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance ^*

Gopal

Garg

Agrawal

et al. 2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

The device behavior of a Stacked Ferroelectric Heterojunction Tunnel FET (Fe-HTFET) on BOX substrate is investigated in this paper. In a stacked gate configuration, Si-doped HfO2 was taken as the ferroelectric material over an oxide layer (gate dielectric). Higher drive current and reduced sub-threshold swings (SS) may be achieved by using a silicon doped HfO2 that amplifies the given gate bias. The effect of various electrical parameters has been investigated by changing the geometric dimensions of the proposed device. The dimensional parameters have been optimized after extensive simulations. The proposed Fe-HTFET simulations and results show that this structure boosts performance significantly and could be considered a good contender for ultra-low-power applications. In order to investigate the performance of the proposed Fe-HTFET, 2-D simulations have been done using Sentaurus TCAD tool.

show abstract

Section: Device Architecture and Simulation Deckmentioning

confidence: 99%

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance ^*

Gopal

Garg

Agrawal

et al. 2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…A recent study has demonstrated the suitability of PTMs in the development of low-power dynamic circuits [5]. Moreover, it has been revealed that combining PTM with the negative capacitance effect improves the sub-threshold slope further and holds great promise for applications in digital devices and memories [6,7].…”

Section: Introductionmentioning

confidence: 99%

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

Sorot,

Goel,

Rewari

2024

Phys. Scr.

View full text Add to dashboard Cite

This research paper introduces a novel design for a Hybrid-CMOS Inverter using Vanadium Dioxide (VO2), a Phase Transition Material. The proposed Inverter exhibits a remarkably steep transition for falling logic at the output (1-0). By leveraging the Insulating to Metallic Current Density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS Inverter, the designed Inverter demonstrates several advantages. It achieves higher values of lower Noise Margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for the design of Inverters at lower Drain voltages, especially in devices operating at lower technology nodes. Furthermore, the Hybrid-CMOS Inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower Noise Margin and reduced values of leakage current.

show abstract

“…Ferroelectric materials-based transistors [13]h a v e gotten a lot of interest recently for their ability to provide ultra-low power in memory and steep switching applications due to the negative capacitance property exhibit by ferroelectric materials. These devices have gotten a lot of interest because of their simpler design and CMOS compatibility [14], compared to other state-of-the-art devices such as TFETs [15], HyperFETs [16], and Hybrid FETs [17][18][19]. In addition, the recognition of ferroelectricity in doped hafnium oxides like HZO [20] has rekindled curiosity in NC based FET.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Yadav

Kondekar

Awadhiya

et al. 2022

Preprint

Self Cite

View full text Add to dashboard Cite

In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14nm conventional FinFET to form NC-FinFET. Static and dynamic behaviour of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET-based SRAM, 6T-NCSRAM exhibits distinct behaviour during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

show abstract

Ferroelectric Negative-Capacitance-Assisted Phase-Transition Field-Effect Transistor

Cited by 10 publications

References 41 publications

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance ^*

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance ^*

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Contact Info

Product

Resources

About

Ferroelectric Negative-Capacitance-Assisted Phase-Transition Field-Effect Transistor

Cited by 10 publications

References 41 publications

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance *

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance *

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Contact Info

Product

Resources

About

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance ^*

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance ^*