Fault Detection Capabilities of Alternating Logic

Reynolds,; Metze,

doi:10.1109/tc.1978.1675011

Cited by 120 publications

(25 citation statements)

References 3 publications

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“…DIVA can recover from permanent faults and design errors in the aggressive processor but assumes that no transient faults occur in the checker processor itself. Other works on fault tolerance focus on functional units [11,7,4,14].…”

Section: Related Workmentioning

confidence: 99%

Transient-fault recovery using simultaneous multithreading

Vijaykumar¹,

Pomeranz²,

Cheng³

Proceedings 29th Annual International Symposium on Computer Architecture

174

101

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Section: Related Workmentioning

confidence: 99%

Transient-fault recovery using simultaneous multithreading

Vijaykumar¹,

Pomeranz²,

Cheng³

Proceedings 29th Annual International Symposium on Computer Architecture

174

101

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“…An alternating encoding scheme as illustrated in Fig. 8 can protect the status bits against delay and transient faults [27]. In Fig.…”

Section: Monitoring Of In-order Pipelinesmentioning

confidence: 99%

Error prediction based on concurrent self-test and reduced slack time

Gherman

Massas

Evain

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Small circuit defects occurred during manufacturing and/or enhanced/induced by various aging mechanisms represent a serious challenge in advanced scaled CMOS technologies. These defects initially manifest as small delay faults that may evolve in time and exceed the slack time in the clock cycle period. Periodic tests performed with reduced slack time provide a low-cost solution that allows to predict failures induced by slowly evolving delay faults. Unfortunately, such tests have limited fault coverage and fault detection latency.Here, we introduce a way to complement or completely replace the periodic testing with reduced slack time. Delay control structures are proposed to enable arbitrarily small parts of the monitored component to switch fast between a normal operating mode and a degraded mode characterized by a smaller slack time. Only two or three additional transistors are needed for each flip-flop in the monitored logic. Micro-architectural support for a concurrent selftest of pipelined logic that takes benefit of the introduced degraded mode is presented as well. Test stimuli are produced on the fly by the last two valid operations executed before each stall cycle. Test result evaluation is facilitated by the replication of the last valid operation during a stall cycle. Protection against transient faults can be achieved if each operation is replicated via stall cycle insertion.

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“…These include alternating logic, proposed by Reynolds and Metze in [2], in which the same circuit was used twice. The implemented function was required to be self-dual and the inputs were applied first normally and then inverted and applied again.…”

Section: : Concurrent Error Detectionmentioning

confidence: 99%

Quadruple time redundancy adders [error correcting adder]

Townsend

Abraham

Swartzlander³

Proceedings. 16th IEEE Symposium on Computer Arithmetic

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This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Triple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% -55% reduction in hardware complexity while incurring a reasonable delay zncrease.

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Fault Detection Capabilities of Alternating Logic

Cited by 120 publications

References 3 publications

Transient-fault recovery using simultaneous multithreading

Transient-fault recovery using simultaneous multithreading

Error prediction based on concurrent self-test and reduced slack time

Quadruple time redundancy adders [error correcting adder]

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