Fast growth of thin multi‐crystalline silicon ribbons by the RST method

Abstract

The ribbon on sacrificial template (RST) process is a ribbon direct-wafering technology with specific ability for high throughput and thin multicrystalline wafer production, in the range of 60-140 μm. Mechanical and electrical properties of the RST material were investigated. Ball on ring and four-point bending tests showed good fracture stress values up to 260 MPa. The conversion efficiency potential for passivated emitter and rear cells (PERC) made out from the RST material, around 16%, is shown to be limited by defects reducing minority carrier lifetime. The interaction between impurities, such as C and transitions metals, with structural defects such as dislocations, results in highly recombinative areas in RST wafers. A model is proposed which shows that the carbon substrate is an important source of carbon contamination in the silicon melt during the growth of the ribbon. This high C contamination can be accompanied by transition metal contamination and can have an influence on the growth stability and on the generation of structural defects, especially if C accumulates in a boundary layer just above the growth interface. The study of the segregation of Sb indicates that the process conditions are close to the case of the diffusive regime near the solid/liquid interface, with a boundary layer thickness of about 70 μm.

Role of Impurities in Silicon Solidification and Electrical Properties Studied by Complementary In Situ and Ex Situ Methods

“…Again, the consequence of the presence of a high C concentration was the formation of SiC precipitates which affected the grain structure and defects. [5] Moreover, the solid-liquid interface observed in situ during solidification by X-ray radiography for sample J shows more grain boundary grooves as compared to the case of samples F or V which is directly related to the fact that more grains are present. Indeed, the presence of more grain boundary grooves at the solid-liquid interface reveals the presence of more grain boundaries as grain boundary grooves are formed at the encounter of a grain boundary with the interface.…”

“…The final grain structure and associated defects (grain boundaries and dislocations) issued from the solidification step are responsible for PV properties for a large part. [4] In this context, impurities play a major role as they not only modify grain nucleation and competition during solidification [5,6] but interact as well with structural defects. [7] The nucleation of new grains during growth can happen either on the crucible walls or on precipitates or impurities in the molten silicon.…”

X-ray Based in Situ Investigation of Silicon Growth Mechanism Dynamics—Application to Grain and Defect Formation

“…However, the repetition of twinning has important consequences for the final grain structure and distribution of crystallographic orientations [31]. Indeed, the importance of twinning in the development of the grain structure has been highlighted for different solidification processes ranging from directional solidification [82] to ribbon growth [33,83,84]. In the past few years, we studied rather extensively twin formation, growth, and its At the level of the edge facets, the measured maximum undercooling is again always lower than 1 K. However, higher values (ranging from 2 × 10 −1 to 8 × 10 −1 K) compared to the undercooling inside grain boundary grooves are measured at the edges.…”

“…However, the repetition of twinning has important consequences for the final grain structure and distribution of crystallographic orientations [31]. Indeed, the importance of twinning in the development of the grain structure has been highlighted for different solidification processes ranging from directional solidification [82] to ribbon growth [33,83,84]. In the past few years, we studied rather extensively twin formation, growth, and its consequences on the final grain structure and defect formation in general [44][45][46]48,50,52,85].…”

Novel RGS materials with high fill factors and no material-induced shunts with record solar cell efficiencies exceeding 16%

“…Indeed typical material production speeds are $650 cm/min for RGS, 5 10 cm/min for RST, and 1 2 cm/min for EFG and SR [9]. However, for a fair comparison of the cost effectiveness of all these ribbon techniques, also the thickness of the obtained wafer has to be taken into account regarding the material saving (here, ribbon technologies such as RST are espe cially distinguished due to the possibility to produce very thin wafer with thicknesses down to 60 mm [9,10]). Hence the RGS process provides cost effective alternative wafer materials for solar cell fabrication.…”