FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA

Many modern applications exhibit a dynamic and non-stationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable FPGA architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx's commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive API, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the SUSAN image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-theart prefetching algorithms, with only a minor energy overhead.Index Terms-FPGA, partial reconfiguration, dynamic configuration prefetching, self-reconfiguring and adaptive platform.

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“…Similar solutions have been proposed in the literature (e.g. [19], [8]). The controller's architecture is depicted in Fig.…”

Section: Contributionsmentioning

confidence: 58%

“…They all use the (now obsolete) Processor Local Bus (PLB). Another PLB design is presented in [8]. Its main focus is on reducing the reconfiguration time overhead, by using techniques such as ICAP overclocking or bitstream compression.…”

Section: A Self-reconfiguring Platformsmentioning

confidence: 99%

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Lifa

Eles

Peng

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…It also shows the several reconfigurations that occur physically on the FPGA, configured via the Internal Configuration Access Port (ICAP), a hard macro present on the latest Xilinx FPGAs. In our case, the ICAP is managed by our controller, FaRM [17]. For instance, let us consider task T2, Inverse Transform.…”

Section: Resultsmentioning

confidence: 99%

“…This information represent tasks deadline, determined by the application specifications, and reconfiguration time overhead. This time overhead can be estimated using the works we lead on an efficient reconfiguration manager coupled with an accurate cost model [17]. The architecture model only needs the targeted device to infer potential reconfigurable zones.…”

Section: A Overview and Design Flowmentioning

confidence: 99%

Methodology for designing partially reconfigurable systems using transaction-level modeling

Duhem

Muller

Lorenzini

2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC. Our approach relies on dynamic threads to change the functionality of modules during runtime and on transaction level modeling for all the communications. We introduce a reconfiguration manager to develop and validate scheduling algorithms for hardware tasks management. Moreover, our simulator performs design space exploration in order to find a viable implementation (in terms of reconfigurable zones) for a given application. Our methodology is validated with the modeling of a dynamically reconfigurable video transcoding chain.

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“…They all use the (now obsolete) Processor Local Bus (PLB). Another PLB design is presented in [DML11]. Its main focus is on reducing the reconfiguration time overhead, by using techniques such as ICAP overclocking or bitstream compression.…”

Section: Partial Dynamic Reconfigurationmentioning

confidence: 99%

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

Lifa¹

2015

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M odern applications running on today's embedded systems have very high requirements. Most often, these requirements have many dimensions: the applications need high performance as well as flexibility, energyefficiency as well as real-time properties, fault tolerance as well as low cost. In order to meet these demands, the industry is adopting architectures that are more and more heterogeneous and that have reconfiguration capabilities. Unfortunately, this adds to the complexity of designing streamlined applications that can leverage the advantages of such architectures.In this context, it is very important to have appropriate tools and design methodologies for the optimization of such systems. This thesis addresses the topic of hardware/software codesign and optimization of adaptive real-time systems implemented on reconfigurable and heterogeneous platforms. We focus on performance enhancement for dynamically reconfigurable FPGA-based systems, energy minimization in multi-mode real-time systems implemented on heterogeneous platforms, and codesign techniques for fault-tolerant systems.The solutions proposed in this thesis have been validated by extensive experiments, ranging from computer simulations to proof of concept implementations on real-life platforms. The results have confirmed the importance of the addressed aspects and the applicability of our techniques for design optimization of modern embedded systems. v vi Populärvetenskaplig Sammanfattning I dag är inbyggda system vanligt förekommande och deras antal fortsätter att öka. De används inom en mängd olika domäner, t.ex. hemelektronik, fordonsindustri, flygelektronik, medicin, etc., och de hittas nästan överallt omkring oss: från våra telefoner, bärbara datorer och tvättmaskiner till våra bilar. De applikationer som körs på dessa system har flera olika ökande krav: högprestanda, energieffektivitet, flexibilitet, feltolerans, realtidsegenskaper, och naturligtvis låg kostnad. För att kunna uppfylla dessa krav har industrin anammat arkitekturer som är mer och mer heterogena och som har omkonfigureringsmöjligheter. Olyckligtvis ökar detta komplexiteten när man ska utforma effektiva inbyggda system. I detta sammanhang blir det av yttersta betydelse att utveckla effektiva optimeringsmetoder och verktyg.Dagens applikationer består av en blandning av mjukvarukomponenter som har mycket olika energi-och prestandaegenskaper beroende på vilka hårdvaruenheter där de körs på, vilket gör dem lämpliga för heterogena plattformar. En heterogen plattform består av olika typer av hårdvaruen-heter, var och en med sina egenskaper, som riktar sig till vissa tillämpn-ingsområden. Under det senaste decenniet har utvecklingen av rekonfigurerbara hårdvarutekniker accelererat, vilket bidrar till den ökande populariteten för fältprogrammerbara grindmatriser (FPGA). Idag, ger hård-varutillverkare stöd för partiell dynamisk omkonfigurering; detta innebär att delar av en FPGA kan konfigureras vid run-time, medan andra delar förblir fullt fungerande. Dessa tekniska framsteg har...

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FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA

Cited by 29 publications

References 6 publications

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Methodology for designing partially reconfigurable systems using transaction-level modeling

Hardware/Software Codesign of Embedded Systems with Reconfigurable and Heterogeneous Platforms

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