2013
DOI: 10.1016/j.microrel.2012.06.140
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Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

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Cited by 69 publications
(36 citation statements)
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“…We also use finite-element (FE) simulations to estimate the stress distribution in Invar-based TSVs and in the surrounding silicon at various temperatures. The stress distribution in an Invar TSVs is compared to the stress distribution in a copperbased TSV structure described in literature [9]. We show that the use of Invar reduces the cracking probability and the carrier mobility drifts in the silicon region surrounding the TSV.…”
Section: Introductionmentioning
confidence: 94%
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“…We also use finite-element (FE) simulations to estimate the stress distribution in Invar-based TSVs and in the surrounding silicon at various temperatures. The stress distribution in an Invar TSVs is compared to the stress distribution in a copperbased TSV structure described in literature [9]. We show that the use of Invar reduces the cracking probability and the carrier mobility drifts in the silicon region surrounding the TSV.…”
Section: Introductionmentioning
confidence: 94%
“…For large numbers of thermal cycles during the lifetime of TSV structures, this stress accumulation can cause delamination and cohesive crack growth, which can in turn result in failure of the electrical contacts [8,9]. Most electronic devices are exposed to numerous thermal cycles during their operating life for different reasons.…”
Section: Introductionmentioning
confidence: 99%
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