2005
DOI: 10.1109/led.2005.854353
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Fabrication and characterization of 100-nm In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As double-gate HEMTs with two separate gate controls

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Cited by 26 publications
(23 citation statements)
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“…Two opposite gate electrodes control the total electron density in the channels as well as the carrier shift between them in DM operation. The only difference with respect to a DG--HEMT [2][3][4][5][6] is that the channel is divided into two regions: a high-µ undoped channel and a low-µ channel…”
Section: Physical Modelmentioning
confidence: 99%
See 1 more Smart Citation
“…Two opposite gate electrodes control the total electron density in the channels as well as the carrier shift between them in DM operation. The only difference with respect to a DG--HEMT [2][3][4][5][6] is that the channel is divided into two regions: a high-µ undoped channel and a low-µ channel…”
Section: Physical Modelmentioning
confidence: 99%
“…To further improve their behavior, alternative solutions based on an evolution of the standard HEMT design have been proposed, as the double-gate (DG) HEMT, a HEMT with two gates placed on each side of the conducting InGaAs channel [2][3][4][5][6]. The progress of the DG-HEMT technology has allowed the design and fabrication of III-V velocity modulation transistors (VMTs) [7,8].…”
Section: Introductionmentioning
confidence: 99%
“…Thus, the double-gate ͑DG͒ HEMT, a HEMT with two gates placed on each side of the conducting InGaAs channel, has been recently developed. [1][2][3][4][5] The progress of the DG-HEMT technology allows the design and fabrication of InP-based velocity modulation transistors ͑VMTs͒. The concept of VMT was proposed by Sakaki 6 in 1982 and the first transistor was realized by Cohen et al 7 in 1997 on a GaAs/AlGaAs heterostructure.…”
Section: Fabrication and Fundamentals Of Operation Of An Inalas/ingaamentioning
confidence: 99%
“…In order to characterize the VMT in differential mode ͑application of different voltages on each gate electrode͒ the first gate metallization ͑gate 1͒ must overlap only one mesa sidewall, while keeping a perfect gate alignment. 3 In order to perform the electrical characterization of our VMTs, we define the DC gate voltages by means of two terms: a common mode bias voltage V Goff that controls the level of depletion under both gates and allows adjusting the total amount of electrons in the channel N T ͑and therefore the drain current level͒ and a differential potential V Gdiff / 2 that modulates the population of the high and low mobility channels. As a result, the gate voltages are defined as follows:…”
Section: Fabrication and Fundamentals Of Operation Of An Inalas/ingaamentioning
confidence: 99%
“…To check this statement, we have calculated the values of fmax for the 100 nm-gate devices. For such a calculation, the unilateral gain is obtained from the Y-parameters of the devices taking into account the gate resistances measured in the real devices [4]- [5]. This is an important point since in the DG-HEMTs the gate resistance is nearly one half that of the standard HEMTs (RG=17 Q/mm and 38 Q/mm, respectively), as it benefits from two gates in parallel.…”
Section: Monte Carlo Modelmentioning
confidence: 99%