Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories

Jadidi, Amin; Arjomand, Mohammad; Tavana, Mohammad Khavari; Kaeli, David; Kandemir, Mahmut; Das, Chita R.

doi:10.1109/dsn.2017.56

Cited by 16 publications

(23 citation statements)

References 22 publications

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“…However, such an operation latency is more likely to withstand inside a cache. Finally, Jadidi et al bypass permanent faults in CPU caches implemented with phase-change memory technology by leveraging data compression and shifting the compressed data within the cache lines [20].…”

Section: Other Workmentioning

confidence: 99%

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

2020

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The ever-increasing parallelism demand of General-Purpose Graphics Processing Unit (GPGPU) applications pushes toward larger and more energy-hungry register files in successive GPU generations. Reducing the supply voltage beyond its safe limit is an effective way to improve the energy efficiency of register files. However, at these operating voltages, the reliability of the circuit is compromised. This work aims to tolerate permanent faults from process variations in large GPU register files operating below the safe supply voltage limit. To do so, this paper proposes a microarchitectural patching technique, DC-Patch, exploiting the inherent data redundancy of applications to compress registers at run-time with neither compiler assistance nor instruction set modifications. Instead of disabling an entire faulty register file entry, DC-Patch leverages the reliable cells within a faulty entry to store compressed register values. Experimental results show that, with more than a third of faulty register entries, DC-Patch ensures a reliable operation of the register file and reduces the energy consumption by 47% with respect to a conventional register file working at nominal supply voltage. The energy savings are 21% compared to a voltage noise smoothing scheme operating at the safe supply voltage limit. These benefits are obtained with less than 2 and 6% impact on the system performance and area, respectively.

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Section: Other Workmentioning

confidence: 99%

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

2020

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“…Fine-Grained Current Regulation (FGCR) [23], which is possible by modifying the PCM's peripheral circuit, reduces the RESET programming power and increases memory lifetime. Employing a DRAM buffer [28], data coding/encoding [4,33,45], wear-leveling algorithms [1,39], and data compression [5,22,36] are among the several competing mechanisms that have been explored to improve PCM lifetime. Although these techniques are effective in prolonging memory lifetimes, error correction mechanisms still need to be included to handle faults due to wear-out.…”

Section: Background and Related Workmentioning

confidence: 99%

Block Cooperation

Tavana

Ziabari

Kaeli

2018

ACM Trans. Archit. Code Optim.

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Block-level cooperation is an endurance management technique that operates on top of error correction mechanisms to extend memory lifetimes. Once an error recovery scheme fails to recover from faults in a data block, the entire physical page associated with that block is disabled and becomes unavailable to the physical address space. To reduce the page waste caused by early block failures, other blocks can be used to support the failed block, working cooperatively to keep it alive and extend the faulty page's lifetime. We combine the proposed technique with existing error recovery schemes, such as Error Correction Pointers (ECP) and Aegis, to increase memory lifetimes. Block cooperation is realized through metadata sharing in ECP, where one data block shares its unused metadata with another data block. When combined with Aegis, block cooperation is realized through reorganizing data layout, where blocks possessing few faults come to the aid of failed blocks, bringing them back from the dead. Our evaluation using Monte Carlo simulation shows that block cooperation at a single level (or multiple levels) on top of ECP and Aegis, boosts memory lifetimes by 28% (37%) and 8% (14%) on average, respectively. Furthermore, using trace-driven benchmark evaluation shows that lifetime boost can reach to 68% (30%) exploiting metadata sharing (or data layout reorganization).

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“…Space Oblivious Compression [54] uses in-place and lightweight compression that is tailored to reduce a NVM's energy, rather than saving space. Jadidi et al [39] exploit memory compression, along with an intra-line wear leveling mechanism, to increase the effectiveness of error correcting codes in NVMs, increasing memory lifetimes. CompEx++ [61] integrates compression with expansion coding to simultaneously improve energy, latency, and lifetimes of MLC NVMs.…”

Section: Prior Work: Secure Non-volatile Memorymentioning

confidence: 99%

“…Memory compression mechanisms can also be used to save energy and/or increase memory lifetimes in encrypted [40], or unencrypted [39,54,61] NVMs. Space Oblivious Compression [54] uses in-place and lightweight compression that is tailored to reduce a NVM's energy, rather than saving space.…”

Section: Prior Work: Secure Non-volatile Memorymentioning

confidence: 99%

“…In an attempt to relax the problem of limited lifetime in PCM, prior studies have proposed techniques that exploit write buffers [50,67], use compression [10,26,39,94], and use encoding schemes [9,38] in order to reduce write traffic in PCM-based memory systems. In parallel, the controller may use wear-leveling techniques (such as Start-and-Gap [65]) in order to uniformly spread the write traffic over all memory blocks, which delays wear-out of some of the memory blocks if they are under high write pressure.…”

Section: Related Workmentioning

confidence: 99%

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Architectural support for designing dependable non-volatile main memories

Tavana¹

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Exploring the Potential for Collaborative Data Compression and Hard-Error Tolerance in PCM Memories

Cited by 16 publications

References 22 publications

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

Block Cooperation

Architectural support for designing dependable non-volatile main memories

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