Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) 2002
DOI: 10.1109/dac.2002.1012646
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Exploiting operation level parallelism through dynamically reconfigurable datapaths

Zhining Huang1,
M. Sharad2
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Cited by 9 publications
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References 5 publications
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Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Mei
1
,
Vernalde
2
,
Verkest
3
et al. 2003
IEE Proc., Comput. Digit. Tech.
97
1
148
0
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Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Mei
1
,
Vernalde
2
,
Verkest
3
et al. 2003
IEE Proc., Comput. Digit. Tech.
97
1
148
0
View full textAdd to dashboardCite

Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling

Mei
1
,
Vernalde
2
,
Verkest
3
et al.
2003 Design, Automation and Test in Europe Conference and Exhibition
108
0
4
0
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Design and validation of execution schemes for dynamically reconfigurable architectures

Oppold1,
Eisenhardt2
2006
2006 IEEE International Conference on Field Programmable Technology
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0
4
0
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