Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits

Ali, Belayet; Almaini, A. E. A.; Kalganova, Tatiana

doi:10.1023/b:genp.0000017009.11392.e2

Cited by 38 publications

(25 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Two groups of benchmarks are adopted in the experiments. One is taken from [12], the other is taken from [41]. Both of them are taken from the MCNC benchmark [45] library.…”

Section: Methodsmentioning

confidence: 99%

“…Generally, the structure of a sequential logic circuit can be demonstrated as Fig. 4 [12]. As is shown in Fig.…”

Section: Basic Concepts About Sequential Logic Circuitsmentioning

confidence: 99%

“…For a small sequential logic circuit, it can be evolved easily using a given set of available logic gates [12]. However, it is difficult to evolve a larger sequential logic circuit directly.…”

Section: Basic Concepts About Sequential Logic Circuitsmentioning

confidence: 99%

See 2 more Smart Citations

A three-step decomposition method for the evolutionary design of sequential logic circuits

Liang

Luo

Wang

2009

Genet Program Evolvable Mach

View full text Add to dashboard Cite

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a threestep decomposition method (3SD). A novel extrinsic EHW system, namely 3SD-ES, which combines the 3SD method with the (l, k) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD-ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.

show abstract

“…Two groups of benchmarks are adopted in the experiments. One is taken from [12], the other is taken from [41]. Both of them are taken from the MCNC benchmark [45] library.…”

Section: Methodsmentioning

confidence: 99%

“…Generally, the structure of a sequential logic circuit can be demonstrated as Fig. 4 [12]. As is shown in Fig.…”

Section: Basic Concepts About Sequential Logic Circuitsmentioning

confidence: 99%

See 1 more Smart Citation

A three-step decomposition method for the evolutionary design of sequential logic circuits

Liang

Luo

Wang

2009

Genet Program Evolvable Mach

View full text Add to dashboard Cite

show abstract

“…The evolutionary algorithm composes the combinational circuits either of elementary gates or high-level functional blocks such as adders, multiplexers or comparators. The evolutionary design of sequential circuits is considerably less mature (see discussion in [5]). However, sequential circuits are crucial for implementation of digital computational devices because they represent the circuit implementation of an abstract concept of the discrete state.…”

Section: Introductionmentioning

confidence: 99%

“…Only in some cases the sequential circuits were evolved. As a typical example, reference [5] describes the evolutionary circuit design for finite state machines (FSM) and counters. Flip-flops, registers, and elementary gates are used as building blocks.…”

Section: Introductionmentioning

confidence: 99%

Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level

Sekanina

Zebulum

2005 NASA/DoD Conference on Evolvable Hardware (EH'05)

View full text Add to dashboard Cite

show abstract

Evolvable hardware design based on a novel simulated annealing in an embedded system

Xiong

Yang

et al. 2012

Concurrency and Computation

View full text Add to dashboard Cite

SUMMARYThe auto-design of electronic circuits for the next generation Information Technology (IT) computing environments is currently one of the most extensively studied issues in the field of evolvable hardware (EHW) architectures. It aims to improve the reliability and fault-tolerance of hardware systems using embedded techniques. As the scalability of logic circuits becomes larger and more complex nowadays, its auto-design is more and more difficult. In order to improve the efficiency and the capability of digital circuit auto-design, in this paper, a multi-objective simulated annealing (MSA)-based increasable evolution approach is proposed in an embedded system. First, an extended matrix encoding method is used to indicate the potential performance of a circuit. Therefore, the risk of deleting a circuit with a good developing potential during evolution can be reduced. Second, we consider each output of a digital circuit as an objective, and MSA is designed for digital logic circuits with gradual evolution scheme. In the process of evolution, each objective is evolved in parallel with adaptive mechanism of neighborhood and a performance evaluation. Finally, a framework of online evolution with macro-blocks is employed to implement MSA on a field-programmable gate array efficiently and securely. In our experiments, six arithmetic circuits are designed to assess the performance of MSA with gate-level and function-level approaches comparing to other algorithms. The comparison results show that our method is very efficient in the auto-design of EHW.

show abstract

Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits

Cited by 38 publications

References 14 publications

A three-step decomposition method for the evolutionary design of sequential logic circuits

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level

Evolvable hardware design based on a novel simulated annealing in an embedded system

Contact Info

Product

Resources

About