Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage

Sekanina, Lukáš; Starecek, L.; Gajda, Zbysek; Kotásek, Zdenĕk

doi:10.1109/ahs.2006.35

Cited by 15 publications

(8 citation statements)

References 5 publications

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“…Another visible advantage of intrinsic EHW is that it can exploit physical properties of the electronic platform or environment (e.g. temperature [2], power supply voltage [3] etc.) and thus to provide some innovative features.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

Wang

Chen

Lee

2008

IET Comput. Digit. Tech.

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The authors present a novel virtual reconfigurable architecture (VRA) for realising real-world applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays (FPGAs). The phenotype representation of the proposed evolvable system is based on a two-dimensional function element (FE) network. Compared with the traditional Cartesian genetic programming, the proposed approach includes more connection restrictions in the FE network to reduce genotype length. Another innovative feature of the VRA is that the whole evolvable system, which consists of an evolutionary algorithm unit, a fitness value calculation unit and an FE array unit, can be realised on a single FPGA. On this work, a custom Xilinx Virtex xcv2000E FPGA, which is fitted in the Celoxica RC1000 Peripheral Component Interconnect (PCI) board is utilised as the hardware platform. The main motive of the research is to design a general, flexible evolvable system with powerful computation ability to achieve intrinsic evolution. As examples, the proposed evolvable system is devoted to evolve two real-world applications: a character recogniser and an image operator by using gate level evolution and function level evolution, respectively. The experimental results show that the VRA can bring higher computational ability and more flexibility than traditional approach to intrinsic EHW.

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Section: Introductionmentioning

confidence: 99%

Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

Wang

Chen

Lee

2008

IET Comput. Digit. Tech.

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“…a single circuit structure can perform two or more logic functions according to the external environment [13,12,5]),…”

Section: Introductionmentioning

confidence: 99%

Physical Demonstration of Polymorphic Self-Checking Circuits

Růžička

Sekanina

Prokop

2008

2008 14th IEEE International on-Line Testing Symposium

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“…addition vs. multiplication) for two different levels of the control variable (e.g. for Vdd = 1.8V and Vdd = 3.3V) of the polymorphic gates [10]. Similarly to [17], instead of two functions, the proposed adder performs only one function -addition; however, by two different implementations which are switched using a control variable during circuit normal operation.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

Sekanina

2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carrypropagate adder which is composed of the proposed 1-bit selftesting adders are investigated.

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Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage

Cited by 15 publications

References 5 publications

Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware

Physical Demonstration of Polymorphic Self-Checking Circuits

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

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