Evaluation Scheme for NoC-based CMP with Integrated Processor Management System

Abstract

Evaluation Scheme for NoC-based CMP with Integrated Processor Management SystemWith the opportunities and benefits offered by Chip Multiprocessors (CMPs), there are many challenges that need to be addressed in order to exploit the full potential of CMPs. Such aspects as parallel programs, interconnection design, cache arrangement and on-chip cores allocation become a limiting factor. To ensure validity of approaches and research, we propose an evaluation system for CMPs with Network-on-Chip (NoC) and processor management system integrated on one die. The suggested experimentation system is described in details. The proposed system that is used for tests and results of the experiments are presented and discussed. As decision making criteria, we consider energy efficiency of Processor Allocator (PA) and NoC, as well as NoC traffic characteristic (load balance). In order to improve the system understanding, brief overview on most important NoC and PA architectures is also presented. Analyzed results reveal that CMP with a PA controlled by IFF allocation algorithm for mesh systems and torus-based NoC driven by DORLB routing with express-virtual-channel flow control achieved the best traffic balance and energy characteristic.

Extended Analysis of Resource Assignment in Modern Chip Multiprocessors

“…The parameters of the simulation are: P 1 -horizontal size of the mesh/torus, P 2 -vertical size of the mesh/torus, P 3 -topology (2D-mesh or 2D-torus), P 4 -flow control (virtual-channel or expressvirtual-channel), P 5 -routing algorithm (DOR, Valiant, DOR-LB, Valiant-LB or Adaptive), P 6 -locations of the PA (coordinates). The output results are: E 1 -virtual channel count, E 2 -express virtual channel count, E 3 -total virtual channel count, E 4 -total express virtual channel count [8].…”

“…In [7], the authors of this paper have presented energy model for NoC-based CMP with an integrated PA. The model was used in [8], where a simulation system was described and experimental results were revealed. Similar computing -communication system was also described and optimized in [9].…”

Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance

“…In contiguous allocation strategy, the PEs allocated to job are physically adjacent and have the same topology like NoC. In this paper we use contiguous processor allocation strategy since it is more effective for CMPs [7], [9].…”

“…A hardware Brought to you by | University of Nevada, Las Vegas Authenticated Download Date | 1/22/15 12:32 AM implementation of PA and JS is described in [7]. For the proposed CMP with embedded PA and JS, an energy model is described in [15] and the performance is evaluated in [9]. In this paper, we present the problem of PA and JS location on the chip and its impact on the NoC and performance of the allocation process.…”

Software Development Approach for Discrete Simulators

“…In this case, the simulation model has to be build (static model may be used as the base model) and results are produced as the output of simulation, which is the process intended to act as close to real working system as possible [13], [14]. On the contrary to static modeling, where the result is ready after solution lookup is done (which can take lots of time in case of big problems), simulation allows observing partial results as they appear in the simulation process [13].…”