Evaluation of graded-channel SOI MOSFET operation at high temperatures

DC and RF temperature behavior of deep submicron Graded Channel MOSFETs

“…Aspects like DC, analog, RF [1]- [3], 1/f and RF noise [4]- [6], linearity [7]- [9] and high temperature [10] show the favoured performance of the Graded-Channel (GC) MOS transistor over the classical MOS transistor. However, the shortest GCMOS reported so far has a channel length of 0.5 µm [6].…”

Effect of high temperature on analog parameters of Asymmetric Self-Cascode SOI nMOSFETs

“…As it can be seen, the subthreshold slope degradation (increase) has a linear increase with the temperature and, for both fixed Ls and LD, this behavior is maintained. As it can be seen, the average difference between extracted data and the theoretical limit for this technology increases from lOmY/dec between 300K and 450K to l8mVldec at 500K, which is due the devices reaching critical temperature, where the maximum channel depletion thickness turns smaller than the silicon layer thickness and they begin to work as partially depleted [10]. For the analysis of analog characteristics, the output conductance was extracted and is shown in Fig 7. At a given bias, the effect of the temperature can be seen, since it promotes the decrease of gD due to the mobility reduction and the reduction of the depletion region near the drain, diminishing the channel length modulation effect [6].…”

“…10, for A-SC with Ls=O.7Sllm and varying LD and LD=O.7Sllm and varying Ls. It can be seen that Avo rises with the temperature until approximately 4S0K and starts degrading at SOOK, result of the critical temperature being reached [10].…”

Analysis of Silicon Thickness Reduction on Analog Parameters of GC GAA SOI Transitors Operating up to 300{degree sign}C

“…With the purpose of decreasing the occurrence of parasitic bipolar effects and keeping the threshold voltage and the parasitic bipolar transistor gain within compatible values, a novel SOI structure named Graded-Channel SOI MOSFET (GC SOI MOSFET) has been designed. This device has an asymmetric channel profile as the channel region is divided into two parts: One, at drain side, with a reduced doping concentration, designated as lightly doped region (length L LD ), and in the other channel side, beside the source, the doping concentration is kept at values normally used in fully-depleted SOI CMOS transistors and this region controls the overall device threshold voltage (V th ) (6)(7)(8).…”