Evaluating the effects of branch prediction accuracy on the performance of SMT architectures

Gonçalves, Ronaldo Augusto de Lara; Pilla, Maurı́cio L.; Pizzol, Guilherme Dal; Santos, Tatiana G. S. dos; Santos, Roberta Oliveira; Navaux, Philippe

doi:10.1109/empdp.2001.905062

Cited by 5 publications

(1 citation statement)

References 24 publications

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“…Due to the fact that confidence estimators [7,8] are able to assess the quality of conditional branch predictions, they have been adopted as building blocks in many applications [17][18][19][20][21]. Confidence estimators are very similar to branch predictors [22][23][24] in the sense that they have to make binary decisions (high-confidence and low-confidence or predicted-taken and predicted-untaken, respectively). Just like branch predictors, confidence estimators have a table of Miss Distance Counters (MDCs) to keep a historical record.…”

Section: Controlling Speculative Executionmentioning

confidence: 99%

The Impact of Speculative Execution on SMT Processors

Kang

Liu

Gaudiot

2007

Int J Parallel Prog

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By executing two or more threads concurrently, Simultaneous MultiThreading (SMT) architectures are able to exploit both Instruction-Level Parallelism (ILP) and Thread-Level Parallelism (TLP) from the increased number of in-flight instructions that are fetched from multiple threads. However, due to incorrect control speculations, a significant number of these in-flight instructions are discarded from the pipelines of SMT processors (which is a direct consequence of these pipelines getting wider and deeper). Although increasing the accuracy of branch predictors may reduce the number of instructions so discarded from the pipelines, the prediction accuracy cannot be easily scaled up since aggressive branch prediction schemes strongly depend on the particular predictability inherently to the application programs. In this paper, we present an efficient thread scheduling mechanism for SMT processors, called SAFE-T (Speculation-Aware Front-End Throttling): it is easy to implement and allows an SMT processor to selectively perform speculative execution of threads according to the confidence level on branch predictions, hence preventing wrong-path instructions 123 362 Int J Parallel Prog (2008) 36:361-385 from being fetched. SAFE-T provides an average reduction of 57.9% in the number of discarded instructions and improves the instructions per cycle (IPC) performance by 14.7% on average over the ICOUNT policy across the multi-programmed workloads we simulate.

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Section: Controlling Speculative Executionmentioning

confidence: 99%

The Impact of Speculative Execution on SMT Processors

Kang

Liu

Gaudiot

2007

Int J Parallel Prog

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Improving SMT performance scheduling processes

Gonçalves

Navaux

Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-Based Processing

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Speculation control for simultaneous multithreading

Kang

Gaudiot²

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.

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Speculative executions help modern processors to expose independent instructions on the fly and accordingly exploit more Instruction-Level Parallelism. However, when incorrect speculations occur, useless work is performed for those incorrectly speculated instructions. This lowers a sustained performance and leads to a significant waste of power. Unlike superscalar processors, Simultaneous Multithreading (SMT) processors can concurrently execute multiple threads. Thus, they have a chance to control speculative executions by deliberately choosing threads from which instructions will be fetched at each cycle, considering the dynamic characteristics of running threads.In this paper, we present an efficient front-end mechanism, called SAFE-T (Speculation-Aware Front-End Throttling), for scheduling threads in SMT processors. It involves thread prioritizing and throttling; priority given to a thread can be overridden when that thread seems to suffer from an excessive amount of incorrect speculations, therefore preventing instructions from being fetched. Simulation results show that our policy provides an average reduction of 41.6% in the number of wrong-path instructions and improves the instruction throughput by up to 14.5%. A cost-effective implementation for the proposed policy is shown as well.0-7695-2132-0/04/$17.00 (C) 2004 IEEE

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Evaluating the effects of branch prediction accuracy on the performance of SMT architectures

Cited by 5 publications

References 24 publications

The Impact of Speculative Execution on SMT Processors

The Impact of Speculative Execution on SMT Processors

Improving SMT performance scheduling processes

Speculation control for simultaneous multithreading

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