Estudo de transistores SOI MOSFETs com camada de silício e óxido enterrado ultrafinos operando em modo de tensão de limiar dinâmica.

Sasaki, K. R. A.

doi:10.11606/t.3.2017.tde-07032017-145408

Cited by 1 publication

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References 15 publications

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“…Redução da barreira de potencial do canal induzida pela tensão aplicada ao dreno.Fonte: Adaptado de Sasaki[49] (2016).…”

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Estudo de transistores de porta tripla (FinFETs) de silício e de germânio.

Oliveira¹

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This work presents an experimental comparison between triple gate FinFETs fabricated on Silicon-On-Insulator (SOI) and on silicon wafers. It is presented the electrical characterization of SOI FinFET and bulk FinFET of both p and n types, in order to compare theirs digital (Current-Voltage curves, threshold voltage, transconductance and subthreshold swing) and analog (intrisic voltage gain, Early voltage, ouput conductance gm/IDS ratio) performances at room temperature (25 °C). Moreover, a temperature evaluation is shown, where its range is from 25 °C to 150 °C. In addition, the studied channel length range is from 130 nm to 10 µm, fin height of 65 nm and the fin width range varying from 20 nm to 250 nm. At room temperature, the SOI FinFET devices show to be more immune to the SCEs than the bulk FinFET ones. However, it is necessary to optimize the SOI structure, since it suffers from the parasitic back interface conduction, which degraded almost all studied parameters, for instance, the subthreshold swing of SOI FinFETs were higher three times (for n-type) and two times (for p-type) compared with the bulk ones. As a result the bulk FinFET is more suitable in analog applications, which presented intrisic voltage gain 10 % and 20% higher than SOI FinFETs, for n-and p-type, respectively. At different temperature the bulk FinFET is more vulnerable to threshold voltage variation than the SOI FinFET. On the other hand, the DIBL is the parameter that tends to be worst as the temperature increases, for the SOI FinFETs. Finally, the basic analog parameters at different temperature operation presented no significant variations, comparing to the ones at room temperature operation. Apart from that, this work also provides a first comparison of the impact of the different Ge-on-Si integration schemes on the Ge pFinFET performances, using Low-Frequency-Noise (LFN) and digital parameters as evaluation tools. It is demonstrated that different substrate growths play a role in the off-state current, where an effort is required in order to optimize (reduce) the drain current level, since has been found that the Ge/Si substrate (from STI last process and relaxed channel) presents a higher defect density into the substrate, resulting in an offcurrent level of one order of magnitude higher than the other processes under evaluation. From the low-frequency-noise results, ones show that there are defects into the channel rather than the gate oxide, which are thermally activated and dominate the subthreshold region. In addition, the strained Ge FinFETs, from both STI first and last processes, which reached values of effective mobility three times higher than the relaxed ones at temperature of 77 K.

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“…Redução da barreira de potencial do canal induzida pela tensão aplicada ao dreno.Fonte: Adaptado de Sasaki[49] (2016).…”

unclassified

Estudo de transistores de porta tripla (FinFETs) de silício e de germânio.

Oliveira¹

View full text Add to dashboard Cite

show abstract

Estudo de transistores SOI MOSFETs com camada de silício e óxido enterrado ultrafinos operando em modo de tensão de limiar dinâmica.

Cited by 1 publication

References 15 publications

Estudo de transistores de porta tripla (FinFETs) de silício e de germânio.

Estudo de transistores de porta tripla (FinFETs) de silício e de germânio.

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