2004
DOI: 10.1063/1.1791758
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Error mechanisms and rates in tunable-barrier single-electron turnstiles and charge-coupled devices

Abstract: Si-based single-electron tunneling (SET) devices have of late become an important alternative to the metal-based ones, both for ultralarge scale integration (ULSI) electronics and for electrical metrology. We have very recently been designing, fabricating, and measuring SET turnstiles, pumps, and charge-coupled devices using tunable barriers in silicon. Having shown the potential of these devices, we wish to understand the error mechanisms which may manifest themselves, and to predict the level of these errors… Show more

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Cited by 30 publications
(18 citation statements)
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“…Universal, analytic results are possible only in special limits, of which a particularly useful one is the statistics of charge capture [52,108,111,124,[145][146][147] (see also an analytic solution for time-limited emission with constant rates in [74,96,148,149]). To model charge capture in a QD by a closing tunable barrier, we follow [147] and consider a close-enough-to-equilibrium initial state of the dot at t = t 0 , when it is well connected to the source lead.…”
Section: Theory Backgroundmentioning
confidence: 99%
See 1 more Smart Citation
“…Universal, analytic results are possible only in special limits, of which a particularly useful one is the statistics of charge capture [52,108,111,124,[145][146][147] (see also an analytic solution for time-limited emission with constant rates in [74,96,148,149]). To model charge capture in a QD by a closing tunable barrier, we follow [147] and consider a close-enough-to-equilibrium initial state of the dot at t = t 0 , when it is well connected to the source lead.…”
Section: Theory Backgroundmentioning
confidence: 99%
“…W (5) and (6) in [123]). For tunnelling, a single-electron WKB approximation for one-dimensional rectangular barrier leads to an estimate of ∆ b as [124,125] …”
Section: Theory Backgroundmentioning
confidence: 99%
“…The "write" operation is accomplished through the SE turnstile, so its operating frequency has a significant effect on the write delay. The transfer accuracy deteriorates if the falling time t fall of the CLK signal is too small [20]; hence, the write delay of the proposed SRAM cell is higher than the read delay. Furthermore, the mechanism of the "write" operation in the proposed memory cell is different from a conventional (CMOS-based) SRAM.…”
Section: A Circuit Performancementioning
confidence: 98%
“…So, the increased voltage levels only appear at this time. Finally, for both simulated cases and by taking into account the transfer error rate of the SE turnstile [20], the frequency of operation for the SRAM cell is given by 166 MHz [20].…”
Section: Simulation Of a Memory Cellmentioning
confidence: 99%
“…Leakage processes in single-electron devices containing MTJs were extensively studied in recent publications [14][15][16][17][18][19][20][21] . Experimental and theoretical investigations 20,22 suggest that in metal single-electron devices with MTJs at moderately high temperatures (≥150 mK) or in the presence of a bias across the junctions (V≥50 µV) the leakage errors are dominated by thermal activation over the Coulomb barrier 20,[23][24][25] .…”
Section: Introductionmentioning
confidence: 99%