Environment for PowerPC microarchitecture exploration

Moudgill, Mayan; Wellman, John-David; Moreno, Jaime H.

doi:10.1109/40.768496

Cited by 96 publications

(57 citation statements)

References 7 publications

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“…In the computer engineering domain, the calibration of performance models is mostly applied in cycle-accurate modeling of system components like processor simulators, e.g., Black and Shen [9] and Moudgill et al [28]. So far, the calibration of high-level performance models that aim at (early) system-level design space exploration has not been widely addressed yet.…”

Section: Related Workmentioning

confidence: 99%

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Pimentel

Thompson

Polstra

et al. 2007

J Sign Process Syst Sign Image

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Abstract. High-level performance modeling and simulation have become a key ingredient of system-level design as they facilitate early architectural design space exploration. An important precondition for such highlevel modeling and simulation methods is that they should yield trustworthy performance estimations. This requires validation (if possible) and calibration of the simulation models, which are two aspects that have not yet been widely addressed in the system-level community. This article presents a number of mechanisms for both calibrating isolated model components as well as a system-level performance model as a whole. We discuss these model calibration mechanisms in the context of our Sesame system-level simulation framework. Two illustrative case studies will also be presented to indicate the merits of model calibration.

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Section: Related Workmentioning

confidence: 99%

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Pimentel

Thompson

Polstra

et al. 2007

J Sign Process Syst Sign Image

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“…An endeavor Turandot simulator [11,12] is further inventive effort which simulates a PowerPC architecture. Along with the aid of simultaneous multithread SMT the project was extended for multicore.…”

Section: Simulation Frameworkmentioning

confidence: 99%

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

Khari¹,

Kumar²,

Le³

et al. 2017

IJCNIS

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Abstract-A variety of technologies in recent years have been developed in designing on-chip networks with the multicore system. In this endeavor, network interfaces mainly differ in the way a network physically connects to a multicore system along with the data path. Semantic substances of communication for a multicore system are transmitted as data packets. Thus, whenever a communication is made from a network, it is first segmented into sub-packets and then into fixed-length bits for flow control digits. To measure required space, energy & latency overheads for the implementation of various interconnection topologies we will be using multi2sim simulator tool that will act as research bed to experiment various tradeoffs between performance and power, and between performance and area requires analysis for further possible optimizations.

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“…In order to get reasonably accurate initial power estimations of each functional unit for this POWER4-like microprocessor design, we combine IBM's cycle-accurate Turandot performance simulator [15] and PowerTimer power modeling tool [16] running benchmark program bzip2. The initial power inputs to the thermal model are the dynamic power values of running bzip2 for each functional unit.…”

Section: Thermally Self-consistent Leak-age Power Calculationmentioning

confidence: 99%

The need for a full-chip and package thermal model for thermally optimized IC designs

Huang

Humenay

Skadron

et al. 2005

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

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Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally selfconsistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip-and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.

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Environment for PowerPC microarchitecture exploration

Cited by 96 publications

References 7 publications

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Calibration of Abstract Performance Models for System-Level Design Space Exploration

Interconnect Network on Chip Topology in Multi-core Processors: A Comparative Study

The need for a full-chip and package thermal model for thermally optimized IC designs

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