Enhanced gate stack stability in GaN transistors with gate dielectric of bilayer SiNx by low pressure chemical vapor deposition

Abstract

We report enhanced gate stack stability in GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs) by using a bilayer SiNx as the gate dielectric. To obtain the bilayer gate dielectric scheme, a thin Si-rich SiNx interlayer was deposited before a high-resistivity SiNx layer by low pressure chemical vapor deposition. The Si-rich SiNx can effectively suppress the trapping phenomenon at the interface of the dielectric/AlGaN barrier. The upper high-resistivity SiNx layer can greatly block the gate leakage current to enable a large gate swing. Compared with the MISHEMTs using a single Si-rich or high-resistivity SiNx layer, the MISHEMTs with a bilayer gate dielectric take the advantages of both, realizing a gate stack with a stable threshold voltage and low leakage current. These results thus present great potential for developing high-performance GaN MISHEMTs using the bilayer SiNx gate dielectric scheme for highly efficient power applications.

Development of Catalytic-CVD SiNx Passivation Process for AlGaN/GaN-on-Si HEMTs

“…The MIS gate device had a circular MIS gate with a diameter of 100 µm, which was surrounded by an ohmic electrode. In Figure 10a,c, the threshold voltage is negatively shifted with increasing refractive index [24,28,29], which indicates that a high-refractive-index film has more positive fixed charges in the MIS gate than the films with lower refractive indices. In comparison with the reference film with a refractive index of 1.90, the flat-band voltage of the device with the film having a refractive index of 2.12 was negatively shifted from −7.7 V to −13 V with smaller flat band voltage hysteresis (Figure 11d).…”

The effects of an LPCVD SiN x stack on the threshold voltage and its stability in AlGaN/GaN MIS-HEMTs

“…When the SN1 interfacial layer is thick enough (here samples D and E), it is reasonable to assume the same SiN x /GaN interface properties as those of sample B with the SN1 single layer. Therefore, more extra positive fixed charges δ SN2 were introduced at the SN1/SN2 interface in samples D and E than in sample C. It was believed that a Fermi-level pinning effect can be induced by such a high density of positive fixed charge (in the order of 10 13 cm −2 ), resulting in better V th stability [28]. Moreover, considering the high resistivity of the near-stoichiometric SN2 capping layer, we speculate that the electric voltage drop across the SiN x /GaN interface was effectively weakened and/or modulated in the optimized bilayer SiN x stack.…”

“…In addition, with increasing thickness of the SN1 interfacial layer from samples C to E, the V th first decreased to the minimum (−17.1 V) for sample D and then increased (−14.5 V) for sample E, exhibiting a non-monotonic relationship with γ. It was believed that high-density positive charges δ SN2 (∼1.1 × 10 13 cm −2 ) can occur at the SN1/SN2 interface due to the high density of dangling bonds between the two SiN x layers during the discontinuous SiN x deposition [28].…”

“…Song et al [27] revealed that the hysteresis of V th and the dynamic performance of AlGaN/GaN MIS-HEMTs can be improved by a Si-rich LPCVD-SiN x passivation layer. Huang et al observed an enhanced V th stability and low gate leakage of AlGaN/GaN MIS-HEMT devices with LPCVD-SiN x bilayer stacks using Si-rich SiN x (2 nm) as an interfacial layer capped with a high-resistivity SiN x (15 nm) layer [28]. SiN x bilayer stacks have presented the potential to enhance the reliability of MIS-HEMTs.…”

A review on the GaN-on-Si power electronic devices

“…9 Issue of gate reliability in GaN-based HEMTs. ( a) I GS ∼ t curves, (b)Weibull distribution of t B [54] , (c) Lifetime prediction for p-GaN E-HEMTs [55] , d, Lifetime prediction for MIS-HFETs [56] , (e) Carrier behaviors in p-GaN gate under positive bias, (f) Gate current components [54] , (g) V th shifts with stress pulse time in p-GaN E-HEMTs [57] , and (h) V th shifts with stress pulse time in MIS-HFETs [58] . …”