Energy-Efficient Real-Time Multi-Core Assignment Scheme for Asymmetric Multi-Core Mobile Devices

Kim, Dong-Hoon; Ko, Young-Bae; Lim, Sung-Hwa

doi:10.1109/access.2020.3005235

Cited by 8 publications

(9 citation statements)

References 17 publications

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“…There are four basic techniques for minimizing power dissipation in embedded electronic systems: voltage scaling, frequency scaling, power gating, and clock gating. As is well known, many theoretical considerations, as well as practical experiments, have shown that the energy consumed by electronic circuits strongly depends on the operating frequency [2,8,9,[15][16][17][18].…”

Section: Related Workmentioning

confidence: 99%

“…Usually, it is a trade-off between energy and system performance [9]. Kim et al [15] presents experiments on ARM's LITTLE real-time architecture that show a strong correlation between the energy and the system performance; its authors try to accommodate real-time task deadlines, working in mobile applications, into the system throughput. Li has made some interesting theoretical considerations in his paper [8] regarding energy and time-constrained task scheduling on multiprocessor computers.…”

Section: Related Workmentioning

confidence: 99%

“…Xie et al [17] proposes a set of task-scheduling algorithms based on the combination of two different approaches, global DVFS (dynamic voltage and frequency scaling called, GDES) that moves tasks to processor slacks, generating minimum dynamic energy consumption, and non-DVFS (NDES), energyefficient scheduling based on the concept of deadline slacks analysis. Eventually, there are some scheduling techniques based on AI algorithms and heuristics, such as machine learning [15] or linear programming [18].…”

Section: Related Workmentioning

confidence: 99%

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An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Antolak

Pułka

2022

Applied Sciences

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The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system's implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications' meeting their other requirements.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Antolak

Pułka

2022

Applied Sciences

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“…The effect of using different styles of coding for balancing between performance and energy consumption of the processing cores is presented in [11]. A core allocation technique to lower the energy usage of mobile devices by engaging the LITTLE cores to a maximum extent and ensuring the performance of the device is proposed in [12]. The execution time of complex programs can be minimized and thus the performance of the applications can be improved by the use of today's high-performance computing systems employing multi-core processors.…”

Section: Literature Reviewmentioning

confidence: 99%

Machine Learning based Electromigration-aware Scheduler for Multi-core Processors

P¹,

Mini²

2022

IJACSA

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The rising performance demands in modern technology devices see the need to pack more functionality per area and are made possible with the advent of technology scaling. The extremely down-scaled, high-density processors used in such technology devices functioning at high frequencies and greater temperatures expedite various aging effects which impact the reliable lifetime of computing systems. Electromigration is considered to be an important intrinsic aging effect that reduces the useful lifetime of modern microprocessors. The objective of this work is to use machine learning methods to develop an electromigration-aware scheduler for assigning workloads to cores based on reliability and performance requirements. Aging estimation of the processor cores is performed based on the proposed computationally efficient and accurate regressionbased thermal prediction models. According to experimental findings, the suggested technique can significantly extend the lifetime of multi-core architectures while allowing performance to degrade gracefully. The maximum error in the prediction of the lifetime of the cores using the proposed methodology is estimated to be 2.85%.

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“…Scheduling typed DAG tasks with real-time constraints on heterogeneous multicore platforms is an emerging research topic. Most of the prior work [3], [9], [16], [18] focuses on scheduling un-typed real-time DAG tasks on heterogeneous platforms, and proposes methods for determining the core type each code segment (i.e., each vertex in a DAG) should be executed on. For typed DAG tasks, Han et al [13] • C.-C. Lin, J. Shi, N. Ueter, M. Günzel and J.-J.…”

Section: Introductionmentioning

confidence: 99%

Type-Aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms

Lin

Shi

Ueter

et al. 2023

IEEE Trans. Comput.

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To utilize the performance benefits of heterogeneous multicore platforms in real-time systems, we need task models that expose the parallelism and heterogeneity of the workload, such as typed DAG tasks, as well as scheduling algorithms that effectively exploit this information. In this paper, we introduce type-aware federated scheduling algorithms for sporadic typed DAG tasks with implicit deadlines running on a heterogeneous multicore platform with two different types of cores. In type-aware federated scheduling, a task can be executed in one of the three strategies: Exclusive Allocation, Semi-Exclusive Allocation, and Sequential and Share. In Exclusive Allocation, clusters of cores of both core types are exclusively allocated to tasks, while cores of only one type are exclusively allocated to tasks in Semi-Exclusive Allocation. The workload of the other type from tasks in Semi-Exclusive Allocation and the workload from tasks in Sequential and Share share the cores that are not exclusively allocated to any task. We prove that our type-aware federated scheduling algorithm has a capacity augmentation bound of 7.25. We also show that no constant capacity augmentation bound can be obtained without Semi-Exclusive Allocation. Compared to the state of the art, the type-aware federated scheduling algorithm achieves better schedulability, especially for task sets with skewed workload.

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Energy-Efficient Real-Time Multi-Core Assignment Scheme for Asymmetric Multi-Core Mobile Devices

Cited by 8 publications

References 17 publications

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

An Analysis of the Impact of Gating Techniques on the Optimization of the Energy Dissipated in Real-Time Systems

Machine Learning based Electromigration-aware Scheduler for Multi-core Processors

Type-Aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms

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