Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems

Abstract

Embedded systems are becoming increasingly common in everyday life and like their general-purpose counterparts, they have shifted towards shared memory multicore architectures. However, they are much more resource-constrained, and as they often run on batteries, energy efficiency becomes critically important. In such systems, achieving high concurrency is a key demand for delivering satisfactory performance at low energy cost. In order to achieve this high concurrency, consistency across the shared memory hierarchy must be accomplished in a cost-effective manner in terms of performance, energy, and implementation complexity. In this paper, we propose EMBEDDED-SPEC, a hardware solution for supporting transparent lock speculation, without the requirement for special supporting instructions. Using this approach, we evaluate the energy consumption and performance of a suite of benchmarks, exploring a range of contention management and retry policies. We conclude that for resource-constrained platforms, lock speculation can provide real benefits in terms of improved concurrency and energy efficiency, as long as the underlying hardware support is carefully configured.

Software-improved hardware lock elision

“…In this section we evaluate the benefit provided by our lock elision schemes using two data structure benchmarks and applications from the STAMP suite (commonly used for evaluating hardware TM implementations [12,24,19]), which consists of eight applications that cover a variety of domains and exhibit different characteristics in terms of transaction lengths, read and write set sizes and amounts of contention. The premise of HLE is to enable simple coarse-grained programming with the performance of fine-grained locks, thus obviating the need for fine-grained locking.…”

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures

“…Prior transactional memory proposals restrict speculative computations to the L1 (or sometimes L2) caches, relying on native cache-coherence protocols to detect conflicts. Some prior proposals for speculative synchronization in embedded devices considered only shared-bus single-cluster architectures [18,5]. While popular for their simplicity, such busbased architectures are inherently not scalable, because the bus becomes overloaded when shared by more than a handful of processors.…”