Energy-efficient acceleration of big data analytics applications using FPGAs

Neshatpour, Katayoun; Malik, Maria; Ghodrat, Mohammad Ali; Sasan, Avesta; Homayoun, Houman

doi:10.1109/bigdata.2015.7363748

Cited by 48 publications

(14 citation statements)

References 17 publications

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“…4) Big Data Analysis acceleration: In [34], a platform for energy-efficient acceleration of big data analytics applications using FPGAs is presented by GMU and UCLA. The proposed scheme analyzes data mining and machine learning algorithms, utilized extensively in big data applications, in a heterogeneous platform that included both CPUs and FPGAs.…”

Section: B Mapreduce 1) Scalable Mapreduce Acceleratormentioning

confidence: 99%

A survey on reconfigurable accelerators for cloud computing

Kachris

Soudris

2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

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Data centers are experiencing an exponential increase in the amount of network traffic that they have to sustain due to cloud computing and several emerging web applications. To face this network load, large data centers are required with thousands of servers interconnected with high bandwidth switches. Current data center, based on general purpose processor, consume excessive power while their utilization is quite low. Hardware accelerators can provide high energy efficiency for many cloud applications but they lack the programming efficiency of processors. In the last few years, there several efforts for the efficient deployment of hardware accelerators in the data centers. This paper presents a thorough survey of the frameworks for the efficient utilization of the FPGAs in the data centers. Furthermore it presents the hardware accelerators that have been implemented for the most widely used cloud computing applications. Furthermore, the paper provides a qualitative categorization and comparison of the proposed schemes based on their main features such as speedup and energy efficiency. Index Terms-reconfigurable computing, hardware accelerator, cloud computing, FPGAs, data centers.

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Section: B Mapreduce 1) Scalable Mapreduce Acceleratormentioning

confidence: 99%

A survey on reconfigurable accelerators for cloud computing

Kachris

Soudris

2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

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“…Specifically, AXI4 allows a burst of up to 256 data transfer cycles with just a single address phase and, therefore, is used for memory mapped interfaces. In addition, AXI4-Stream allows an unlimited size of burst data and removes the memory address phase requirement altogether; however, due to their lack of address phases, AXI4-Stream interfaces and transfers are not considered to be memory-mapped [18]. Another approach would be the construction of systems that lead to the combination of AXI memory mapped IP and enhance it with AXI4-Stream.…”

Section: Fpga Bitstreammentioning

confidence: 99%

A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Tsiktsiris

Ziouzios

Dasygenis³

2018

Technologies

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Most frequently, an FPGA is used as an implementation platform in applications of graphics processing, as its structure can effectively exploit both spatial and temporal parallelism. Such parallelization techniques involve fundamental restrictions, namely being their dependence on both the processing model and the system’s hardware constraints, that can force the designer to restructure the architecture and the implementation. Predesigned accelerators can significantly assist the designer to solve this problem and meet his deadlines. In this paper, we present our accelerators for Grayscale and Sobel Edge Detection, two of the most fundamental algorithms used in digital image processing projects. We have implemented those algorithms with a “bare-metal” VHDL design, written purely by hand, as a portable USB accelerator device, as well as an HLS-based overlay of a similar implementation designed to be used by a Python interface. The comparisons of the two architectures showcase that the HLS generated design can perform equally to or even better than the handwritten HDL equivalent, especially when the correct compiler directives are provided.

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“…In this paper we present a novel approach focusing both on performance and power consumption of the recently released Zynq device, for alternating least squares learning algorithm which is an extension of least squares algorithm, with the second one having somewhat more applications in modern computing. Our prototype cluster is almost identical with the one presented here [14] and here [15], except from the fact that we used the Pynq Boards instead of ZedBoards and Apache Spark, instead of Hadoop. Furthermore in our case the bitstream can be downloaded at runtime, as long as it is stored in the boards SD card, using a module that comes with Pynq's image.…”

Section: Related Workmentioning

confidence: 99%

Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering

Katsantonis¹,

Kachris²,

Soudris³

2018

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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Recommendation engines are widely used in order to predict the rating that a user would give to an item based on the user's past behavior. Modern recommendation engines are based on computational intensive algorithms like collaborative filtering that needs to process huge sparse matrices in order to provide efficient results. This paper presents a novel scheme for the acceleration of Alternating Least Squares-based (ALS) collaborative filtering for recommendation engines that can be used to speedup significantly the processing time and also reduce the energy consumption of computing platforms. The proposed scheme is implemented in reconfigurable logic and is mapped to the Pynq platform that is based on an all-programmable MPSoC Zynq system. The hardware acceleration is integrated with the Spark framework and evaluated on real benchmarks from movielens. The performance evaluation shows that the proposed scheme can achieve up to 120x kernel speedup and up to 12x energy-efficiency compared to the embedded ARM processor of Zynq.

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Energy-efficient acceleration of big data analytics applications using FPGAs

Cited by 48 publications

References 17 publications

A survey on reconfigurable accelerators for cloud computing

A survey on reconfigurable accelerators for cloud computing

A High-Level Synthesis Implementation and Evaluation of an Image Processing Accelerator

Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering

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