Energy calculation for periodic multi-core scheduling in system thermal steady state with consideration of leakage and temperature dependency

Fan, Ming; Rong, Rong; Liu, Shuo; Quan, Gang

doi:10.1007/s11227-015-1405-0

Cited by 7 publications

(18 citation statements)

References 19 publications

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“…A speed schedule S is constituted by several state intervals, which is described as below: Definition 1 [25]: Given a speed schedule S for a multi-core system, an interval [t q−1 , t q ] is called a state interval if each core runs only at one mode during that interval.…”

Section: Multi-core Platform and Task Modelmentioning

confidence: 99%

“…According to Definition 1, a speed schedule S essentially consists of a number of nonoverlapped state intervals. Let Q represent the number of non-overlapped state intervals within one scheduling period of S, then we have that [25] 1. ∪ q=1 …”

Section: Multi-core Platform and Task Modelmentioning

confidence: 99%

“…Theorem 1 [25]: Given a periodic speed schedule S(t), let T(L) and T(t q ) be the temperatures at time instant L and t q , t q ∈ [0,L], respectively. If for each eigenvalue λ i of K, we have |λ i | < 1, then the steady-state temperature corresponding to t q can be formulated as…”

Section: Temperature Analysis In System Thermal Steady Statementioning

confidence: 99%

“…Corollary 1 [25]: Given a periodic speed schedule S(t) consisting of Q state intervals, let T 0 be the initial temperature. Then the energy consumption within the q-th state interval in the n-th scheduling period, denoted as E(t q−1 + nL, t q + nL), can be calculated as …”

Section: Real-time Systems 66mentioning

confidence: 99%

“…Theorem 2 [25]: Given a state interval [t q−1 , t q ], let T q−1 be the temperature at time t q−1 . Then the overall system energy consumption within interval [t q−1 , t q ] can be formulated as…”

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Real-Time Systems

Fan¹

2016

Real-Time Systems

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Since 2004, most of chip vendors have begun to shift their major focus from singlecore to multi-core architecture (W. Wolf. Signal Processing Magazine, IEEE, 26(6):50-54, 2009). One major reason of this shift is that it reaches a physical limit by scaling transistor size and increasing the clock frequency to improve the computing performance on a single-core architecture (Agarwal et al. Proceedings of the 27th International Symposium on, pages 248-259, June 2000), that is, the overall chip cannot be reached within a single clock cycle. Multi-core architecture, however, brings innovative and promising opportunities to further improve the computing performance. By providing multiple processing cores on a single chip, multi-core systems can dramatically increase the computing performance and mitigate the power and thermal issues with the same performance achievement as single-core systems. As multi-core architecture has been more and more dominant in the industrial market, there is an urgent demand for effective and efficient techniques for the design of multi-core systems.In this chapter, we first analyze the thermal behavior on multi-core real-time systems by taking the heat transfer among different cores into consideration. Then we analyze the energy consumption for a given speed scheduling on multi-core systems.

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Section: Multi-core Platform and Task Modelmentioning

confidence: 99%

Section: Multi-core Platform and Task Modelmentioning

confidence: 99%

Section: Temperature Analysis In System Thermal Steady Statementioning

confidence: 99%

Section: Real-time Systems 66mentioning

confidence: 99%

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