Energy-Aware FPGA-based Architecture for Wireless Sensor Networks

Grassi, Paolo Roberto; Sciuto, D.

doi:10.1109/dsd.2012.50

Cited by 5 publications

(3 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [10], [11], [12] the use of a new generation of flash-based FPGA devices is analyzed. It is shown that the energy consumption WSN node can be reduced below 4 mW.…”

Section: E Power Managementmentioning

confidence: 99%

Challenges in the design of the MAC protocols for wireless sensor networks using VHDL

Kaljić

Aksamovic

2014

2014 X International Symposium on Telecommunications (BIHTEL)

View full text Add to dashboard Cite

In the design of MAC protocols for wireless sensor networks (WSN) it is necessary to fulfill some requirements such as low energy consumption, scalability, simplicity, etc. These requirements are not easy to fulfill from the viewpoint of implementation on FPGA or ASIC technologies. Therefore, in this paper we identify some challenges encountered during the design of MAC protocol for WSN. For some of these challenges, potential solutions are discussed. To illustrate the proposed solutions S-MAC protocol is chosen. VHDL design of the S-MAC protocols is experimentally verified on the Altera EP2C5 FPGA development system.

show abstract

“…In [10], [11], [12] the use of a new generation of flash-based FPGA devices is analyzed. It is shown that the energy consumption WSN node can be reduced below 4 mW.…”

Section: E Power Managementmentioning

confidence: 99%

Challenges in the design of the MAC protocols for wireless sensor networks using VHDL

Kaljić

Aksamovic

2014

2014 X International Symposium on Telecommunications (BIHTEL)

View full text Add to dashboard Cite

show abstract

“…Those programmable logic units are commonly used in embedded space to take over some workloads that cannot be efficiently processed by MCUs. For instance, many battery-powered wireless sensors [38,39] benefit from FPGAs to accelerate their computation-heavy tasks, while maintaining low-cost and low-power characteristics of the system. Furthermore, embedded platforms such as discontinued AT91CAP7 series could provide native MCUand-FPGA integration as a complete solution with metal programmable cell fabric [40] and faster communication interfaces [41].…”

Section: Cost Considerationsmentioning

confidence: 99%

Hardware‐assisted remote attestation design for critical embedded systems

Geden

Rasmussen

2023

IET Information Security

View full text Add to dashboard Cite

Remote attestation, as a challenge-response protocol, enables a trusted entity, called verifier, to ask a potentially infected device, called prover, to provide integrity assurance about its internal state. Remote attestation is becoming increasingly vital for embedded systems that serve in many critical domains, as part of health, military, transportation and industry services, but still lack the most security features available to high-end systems. In most attestation techniques, the prover provides a cryptographic checksum of its static memory contents, that is, code segments, to the verifier when requested to demonstrate that the device is loaded with the right software. However, those measurements are subject to two limitations. First, they cannot guarantee that the prover has always had legitimate software in the memory prior to attestation. This is because occasional measurements, triggered by the verifier, still leave the device vulnerable to the compromise between two attestation windows as a time-of-check-to-time-of-use (TOCTOU) problem. Second, including dynamic memory regions in the checksum calculation is not helpful in practice, since the verifier typically does not know what those regions should contain or which checksums should be accepted as valid. Hence, many attack scenarios residing in those dynamic regions (e.g. stack) would also go unnoticed. To reveal attack scenarios exploiting the memory regions and time windows left unattested, we propose an attestation scheme that can continuously monitor both static and dynamic memory regions with better spatial and temporal attestation coverage. Our monitoring mechanism is designed to be performed in real time using a novel hardware security module (HSM) connected to the prover's system bus. The proposed HSM monitors not only the integrity of the code on the prover but also its execution by checking the compliance of the bits seen on the bus according to a runtime integrity model (RIM) of the prover's software. Therefore, our attestation scheme is capable of reporting scenarios that violate both the (static) code and (dynamic) runtime integrity since the deployment time. K E Y W O R D S embedded systems, protocols, security | INTRODUCTIONRemote attestation aims to address these risks by providing reports on the integrity of a device to a remote entity. A remote attestation scheme generally consists of two parties. Prover, as a potentially infected device, has to assure a remote party called verifier that the device is in a benign state. In a typical attestation scheme, the verifier makes a request to the prover with a challenge. Then, the prover performs some measurements on its memory and returns it as a signed response. Upon receiving the response, if satisfied with its freshness, integrity and authenticity, the verifier can then decide whether the prover is in a legitimate state using the measurement returned.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction ...

show abstract

“…Thus, at least one of the two power-hungry devices, either the FPGA or the transceiver, has to be enabled all the time. Even refinements which use very simple timekeeping on the RCU, such as employing inverter ring-based oscillators [Grassi2012] to power up the receiver periodically at pre-agreed times for data reception, are still sub-optimal: Due to the large timing inaccuracy (drift) of these oscillators, the power-down phases have to be conservatively shortened, leading to the system drawing higher power for longer intervals.…”

Section: Rcu-based Motesmentioning

confidence: 99%

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Engel

Koch

Siebel

2015

2015 IEEE 40th Local Computer Networks Conference Workshops (LCN Workshops)

View full text Add to dashboard Cite

Die Veröffentlichung steht unter folgender Creative Commons Lizenz: Namensnennung -Keine kommerzielle Nutzung -Keine Bearbeitung 4.0 International https://creativecommons.org/licenses/by-nc-nd/4.0 Erklärung zur DissertationHiermit versichere ich, die vorliegende Dissertation ohne Hilfe Dritter nur mit den angegebenen Quellen und Hilfsmitteln angefertigt zu haben. Alle Stellen, die aus Quellen entnommen wurden, sind als solche kenntlich gemacht. Diese Arbeit hat in gleicher oder ähnlicher Form noch keiner Prüfungsbehörde vorgelegen. Darmstadt, den 22.11.2016 (Andreas Engel) AbstractWireless Sensor Networks (WSNs) combine embedded sensing and processing capabilities with a wireless communication infrastructure, thus supporting distributed monitoring applications. WSNs have been investigated for more than three decades, and recent social and industrial developments such as home automation, or the Internet of Things, have increased the commercial relevance of this key technology. The communication bandwidth of the sensor nodes is limited by the transportation media and the restricted energy budget of the nodes. To still keep up with the ever increasing sensor count and sampling rates, the basic data acquisition and collection capabilities of WSNs have been extended with decentralized smart feature extraction and data aggregation algorithms. Energy-efficient processing elements are thus required to meet the ever-growing compute demands of the WSN motes within the available energy budget.The Hardware-Accelerated Low Power Mote (HaLoMote) is proposed and evaluated in this thesis to address the requirements of compute-intensive WSN applications. It is a heterogeneous system architecture, that combines a Field Programmable Gate Array (FPGA) for hardware-accelerated data aggregation with an IEEE 802.15.4 based Radio Frequency System-on-Chip for the network management and the top-level control of the applications. To properly support Dynamic Power Management (DPM) on the HaLoMote, a Microsemi IGLOO FPGA with a non-volatile configuration storage was chosen for a prototype implementation, called Hardware-Accelerated Low Energy Wireless Embedded Sensor Node (HaLOEWEn). As for every multi-processor architecture, the inter-processor communication and coordination strongly influences the efficiency of the HaLoMote. Therefore, a generic communication framework is proposed in this thesis. It is tightly coupled with the DPM strategy of the HaLoMote, that supports fast transitions between active and idle modes. Low-power sleep periods can thus be scheduled within every sampling cycle, even for sampling rates of hundreds of hertz.In addition to the development of the heterogeneous system architecture, this thesis focuses on the energy consumption trade-off between wireless data transmission and insensor data aggregation. The HaLOEWEn is compared with typical software processors in terms of runtime and energy efficiency in the context of three monitoring applications. The building blocks of these applications comprise hardware-acce...

show abstract

Energy-Aware FPGA-based Architecture for Wireless Sensor Networks

Cited by 5 publications

References 8 publications

Challenges in the design of the MAC protocols for wireless sensor networks using VHDL

Challenges in the design of the MAC protocols for wireless sensor networks using VHDL

Hardware‐assisted remote attestation design for critical embedded systems

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Contact Info

Product

Resources

About