Emerging silicon-on-nothing (SON) devices technology

Monfray, S.; Skotnicki, T.; Fenouillet-Béranger, C.; Carriere, N.; Chanemougame, D.; Morand, Y.; Descombes, S.; Talbot, A.; Dutartre, D.; Jenny, C.; Mazoyer, P.; Palla, R.; Leverd, F.; Friec, Y. Le; Pantel, R.; Borel, S.; Louis, D.; Buffet, N.

doi:10.1016/j.sse.2003.12.013

Cited by 44 publications

(18 citation statements)

References 3 publications

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“…The fact that the dry etching selectivity of SiGe versus Si increases as the Ge content increases [9] has led to the adoption of Si 0.7 Ge 0.3 layers in the SON process [5,6]. We have therefore decided to determine for Ge concentrations either equal to 20% or 31% the critical thickness for plastic relaxation in 3 periods {SiGe/Si} superlattices grown on bulk Si(0 0 1).…”

Section: Resultsmentioning

confidence: 99%

“…Amongst such architectures are ultra-thin fully depleted siliconon-insulator (SOI) FETs [1,2], double-gate FETs [3], O-FETs [4], silicon-on-nothing (SON) FETs [5,6], multi-bridge-channel (MBC) FETs [7,8], etc. The latter two approaches rely on the epitaxy of SiGe/Si multilayers, on the formation of trenches and most importantly on the high degree of selectivity (versus Si) that can be achieved when dry etching laterally the SiGe layers (with Ge contents above 15%) [9].…”

Section: Introductionmentioning

confidence: 99%

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Growth of SiGe/Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors

Hartmann¹,

Holliger²,

Laugier³

et al. 2005

Journal of Crystal Growth

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Growth of SiGe/Si superlattices on silicon-on-insulator substrates for multi-bridge channel field effect transistors

Hartmann¹,

Holliger²,

Laugier³

et al. 2005

Journal of Crystal Growth

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“…Moreover, it is difficult to obtain the silicon layer with defect-free crystalline quality due to the ion-implantation damage or the defects occur during the epitaxial growth. Recently, a silicon-on-nothing (SON) transistor, which has a void under the transistor region, has been proposed as one of the ideal structure of SOI, because the dielectric constant at the region below the transistors could be with this structure [6][7][8][9][10][11][12][13][14]. SON structure was originated from the capability of selectively removing SiGe alloys against Si.…”

Section: Introductionmentioning

confidence: 99%

Selective Chemical Wet Etching of Si_0.8Ge_0.2/Si Multilayer

Kil¹,

Yang²,

Kang³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We investigate the effect of the ageing time and etching time on the etching rate of SiGe mixed etching solution, namely 1 vp HF (6%), 2 vp H 2 O 2 (30%) and 3 vp CH 3 COOH (99.8%). For this etching solution, we found that the etch rate of SiGe layer is saturated after the ageing time of 72 hours, and the selectivity of Si 0.8 Ge 0.2 layer and Si layer is 20:1 at ageing time of 72 hours. The collapse was appeared at the etching time of 9min with etching solution of after saturation ageing time.

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“…SiGe as sacrificial layer in combination with selective etching has been investigated because of its potential for various applications, e. g. for Micro Electro Mechanical Systems (MEMS) or for Silicon on Nothing (SON) structures [1][2][3][4]. Different techniques have been applied for the etching of SiGe selectively to Si including Electron Cyclotron Resonance (ECR) plasma etching [5], chemical etching [6] or microwave initiated etching using radicals [2].…”

Section: Introductionmentioning

confidence: 99%