Emerging silicon and non-silicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications (invited paper)

Chau, R.; Brask, Justin; Datta, Suman; Dewey, G.; Doczy, M.; Doyle, B.S.; Kavalieros, J.; Jin, B.; Metz, M.; Majumdar, Amlan; Radosavljević, M.

doi:10.1109/vtsa.2005.1497062

Cited by 12 publications

(4 citation statements)

References 21 publications

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“…Not at all! Rather, it means that the proper technology to incorporate these structures into high performance devices has not been utilized in most cases (but, the reader should look at the cases where this has been done [16]). Moreover, we also need to remember that there is a third important factor in increasing chip device density, and that is clever circuit design, and it is here that the real strength of the nanowires may appear.…”

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confidence: 99%

Quo Vadis Nanoelectronics?

Ferry

2008

Phys. Status Solidi (c)

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Semiconductor devices continue to be downscaled on a regular basis as technology provides the ability to make smaller dimensions via improved lithography, a process which is known as Moore's Law. However, the driving force for the continued increase in number of devices on a chip is not this reduction in size, but the ability to put more functions on a chip with the same cost per unit area of Si. Nevertheless, it is not clear that our technology for Si devices can continue to work much longer. Here, I will discuss the driving forces, including energy dissipation, speed, area, and technological factors for the projected end‐of‐the roadmap technology. Yet, there continues to be a search for new device technologies to supplement, or replace, Si CMOS. Quantum wires have been sug‐gested in many places as a possible new technology that can provide many opportunities for enhancing chip architecture. But, the constraints on any new technology can be viewed in terms of Si cost, and the manner in which new approaches to devices can be pursued will be dis‐cussed. Some possible technologies are FinFETs, vertical quantum wires, carbon nanotubes, III‐Vs, and similar ap‐proaches. Device downsizing is only one of three driving forces that lead to Moore's Law, with increasing chip size and circuit cleverness playing an equal part. This suggests that many novel devices should not be viewed as competition to CMOS, but in the light of how they may modify the circuit architecture. Indeed, circuit clev‐erness has been as important in managing breakthroughs in the past as new processing technology. Some new op‐portunities, that arise from the nature of nanowire fabri‐cation, in these novel devices may lead to breakthroughs in the area of circuit cleverness. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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confidence: 99%

Quo Vadis Nanoelectronics?

Ferry

2008

Phys. Status Solidi (c)

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“…In addition, the Vapor-Liquid-Solid (VLS) grown nanowire may have different interface properties as compared to the etched surfaces of a small cross-section FinFET. Figure 2 shows CV/I vs gate length comparison of Si nanowire pFETs with conventional Si MOSFETs [10]. Comparison of drain current normalized to gate capacitance for a Ge nanowire FET similar to those in Figure 1 can be found in [12].…”

Section: Semiconductor Nanowire Fetmentioning

confidence: 82%

“…Various methods have been employed: (a) normalize the drive current to an equivalent device width of 2d, where d is the diameter of the nanotube [6,7], (b) normalize the drive current to the gate capacitance [8], (c) compare gate delay metric CV/I at the same I on /I off [9] or at the same gate length [10]. Method (a) accounts for device density differences but it couples the nanotube diameter with current drive in a way that is not related to the transport physics.…”

Section: Performance Benchmarkingmentioning

confidence: 99%

“…Method (b) and Method (c) account for differences in gate capacitance and circuit loading but ignore device density considerations [11]. Figure 1 - Figure 3 show examples of CNFET benchmarking [9,10,12,13] according to the three methods above. These and other recent experimental data [14,15] show that the CNFET is at least about 2 -3 times better than Si MOSFETs benchmarked in all the methods described above.…”

Section: Performance Benchmarkingmentioning

confidence: 99%

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Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts

Wong¹

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.

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As device sizes approach the nanoscale, new opportunities arise from harnessing the physical and chemical properties at the nanoscale. Chemical synthesis, self-assembly, and templated self-assembly promise the precise fabrication of device structures or even the entire functional entity. Quantum phenomena and onedimensional transport may lead to new functional devices with very different power/performance tradeoffs. New materials with novel electronic, optical, and mechanical properties emerge as a result of the ability to manipulate matter on a nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper will give an overview of the materials, technology, and device opportunities in the nanoscale era. The focus of discussion will be on nanotubes, nanowires, molecular devices, and novel device concepts for nanoelectronics.

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Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

et al. 2014

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In this letter we report the efficacy of a hydrogen plasma pretreatment for integrating atomic layer deposited (ALD) high-k dielectric stacks with device-quality p-type GaSb(001) epitaxial layers. Molecular beam eptiaxy-grown GaSb surfaces were subjected to a 30 minute H2/Ar plasma treatment and subsequently removed to air. High-k HfO2 and Al2O3/HfO2 bilayer insulating films were then deposited via ALD and samples were processed into standard metal-oxide-semiconductor (MOS) capacitors. The quality of the semiconductor/dielectric interface was probed by current-voltage and variable-frequency admittance measurements. Measurement results indicate that the H2-plamsa pretreatment leads to a low density of interface states nearly independent of the deposited dielectric material, suggesting that pre-deposition H2-plasma exposure, coupled with ALD of high-k dielectrics, may provide an effective means for achieving high-quality GaSb MOS structures for advanced Sb-based digital and analog electronics.

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Emerging silicon and non-silicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications (invited paper)

Cited by 12 publications

References 21 publications

Quo Vadis Nanoelectronics?

Quo Vadis Nanoelectronics?

Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts

Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

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