Embedded Deterministic Test

Rajski, J.; Tyszer, Jerzy; Kassab, Mark; Mukherjee, Nilanjan

doi:10.1109/tcad.2004.826558

Cited by 450 publications

(84 citation statements)

References 33 publications

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“…Papers on various industrial 3D chips have indeed confirmed this practice [41,42]. This comes with an area penalty, and hence the number of extra probe pads should be minimized; on-chip DfT such as Reduced Pin-Count Testing (RPCT) [43] and Test Data Compression [44] can help with this.…”

Section: External Test Access: Probe Accessmentioning

confidence: 97%

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Marinissen

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D-and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D-and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.

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Section: External Test Access: Probe Accessmentioning

confidence: 97%

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Marinissen

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…As pointed out in [16], symbol-based schemes (e.g., [4,17]) can efficiently exploit correlations in the specified bits and do not require ATPG constraints, while linear techniques (e.g., [9,10]) is easy for implementation. In this work, we mainly target symbol-based test compression schemes.…”

Section: Prior Work In Test Data Compressionmentioning

confidence: 99%

A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment

Liu

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Efficient test compression techniques are available, for example, the SmartBIST in [11] and the embedded deterministic test (EDT) in [13]. Both techniques achieve very high encoding efficiency by binding the ATPG algorithm with the test decompression hardware; however, this makes them inappropriate for applications where the fully or partially specified test set is finalized and cannot be modified.…”

Section: Test Compressionmentioning

confidence: 99%

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

Lin¹,

Wu²,

Huang³

2008

2008 17th Asian Test Symposium

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This paper presents PHS-Fill, an ATPG technique that reduces (1) power supply noise for scan-based at-speed testing, and (2) test data volume in a Huffman coding based test compression environment. PHS-Fill first identifies the preferred Huffman symbols; these symbols correspond to the test pattern templates that improve test compression and reduces power supply noise at the same time. ATPG then biases its primary input assignments so that the test pattern blocks match the preferred symbols whenever possible. Simulation results on ISCAS89 and ITC99 benchmark circuits show that PHS-Fill is a promising solution.

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Embedded Deterministic Test

Cited by 450 publications

References 33 publications

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs

A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

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