Electrical Characterization of highly stable 10nm triple-gate FinFET for different contacts and oxide region materials

Madhavi, Kalasapati Bindu; Tripathi, Suman Lata

doi:10.1007/s12633-022-01935-w

Cited by 6 publications

(3 citation statements)

References 27 publications

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“…Te proposed HSICA is compared with the other transformbased HSICA [16][17][18][19][20][21][22][23] [16] 3D-SPIHT [17] 3D-WBTC [18] 3D-LSK [19] 3D-NLS [20] 3D-LMBTC [21] 3D-LCBTC [22] 3D-ZM-SPECK [23] 3D-LEZSPC 3D-SPIHT [17] 3D-WBTC [18] 3D-LSK [19] 3D-NLS [20] 3D-LMBTC [21] 3D-LCBTC [22] 3D-ZM-SPECK [23] 3D-LEZSPC (f ) Figure 1: PSNR (in db) comparison of 3D-LEZSPC with 3D-SPECK [16], 3D-SPIHT [17], 3D-WBTC [18], 3D-LSK [19], 3D-NLS [20], 3D-LMBTC [21], 3D-LCBTC [22], and 3D-ZM-SPECK [23] at various bit rates for the four diferent hyperspectral images. [32,33]. Te pixel depth (bit depth) of Hyperspectral Image I is 14 bits while the pixel depth of Hyperspectral Image II, II, and IV is 16 bits.…”

Section: Methodsmentioning

confidence: 99%

Curvelet Transform Based Compression Algorithm for Low Resource Hyperspectral Image Sensors

Bajpai

Sharma²,

Alam

et al. 2023

Journal of Electrical and Computer Engineering

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The wavelet transform is widely used in the task of hyperspectral image compression (HSIC). They have achieved outstanding performance in the compression of a hyperspectral (HS) image, which has attracted great interest. However, transform based hyperspectral image compression algorithm (HSICA) has low-coding gain than the other state of art HSIC algorithms. To solve this problem, this manuscript proposes a curvelet transform based HSIC algorithm. The curvelet transform is a multiscale mathematical transform that represents the curve and edges of the HS image more efficiently than the wavelet transform. The experiment results show that the proposed compression algorithm has high-coding gain, low-coding complexity, at par coding memory requirement, and works for both (lossy and lossless) compression. Thus, it is a suitable contender for the compression process in the HS image sensors.

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Section: Methodsmentioning

confidence: 99%

Curvelet Transform Based Compression Algorithm for Low Resource Hyperspectral Image Sensors

Bajpai

Sharma²,

Alam

et al. 2023

Journal of Electrical and Computer Engineering

Self Cite

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“…Static random access memory (SRAM) is used as CPU cache memory, occupying over half of the System-on-Chip (SoC) die area. The high density of SRAM with nanosized transistors is vulnerable to variability due to process variations and short-channel effects such as drain-induced barrier lowering (DIBL), non-ideal subthreshold swing ( SS ), and threshold voltage (V th ) roll-off [ 1 , 2 , 3 , 4 ]. The fin field-effect transistor (FinFET)-based SRAM has been adopted to overcome the problems of planar SRAM [ 5 ].…”

Section: Introductionmentioning

confidence: 99%

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Bang

Lee

et al. 2023

Micromachines

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We comprehensively investigate displacement-defect-induced current and static noise margin variations in six-transistor (6T) static random access memory (SRAM) based on a 10 nm node fin field-effect transistor (FinFET) using technology computer-aided design (TCAD). Various defect cluster conditions and fin structures are considered as variables to estimate the worst-case scenario for displacement defects. The rectangular defect clusters capture more widely distributed charges at the fin top, reducing the on- and off-current. The read static noise margin (RSNM) is the most degraded in the pull-down transistor during the read operation. The increased fin width decreases the RSNM due to the gate field. The current per cross-sectional area increases when the fin height decreases, but the energy barrier lowering by the gate field is similar. Therefore, the reduced fin width and increased fin height structure suit the 10 nm node FinFET 6T SRAMs with high radiation hardness.

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“…Power consumption is the most significant challenge to continue MOSFET scaling because of physical limitations to scale subthreshold swing (SS) below 60 mV/decade at 300 K [1][2][3]. Even with FinFET [4][5][6][7] or double-gate MOSFETs, SS is larger than 60 mV/decade. To overcome this limit, many super steep switching devices have been proposed, such as negative capacitance field effect transistors (FETs) [8], nanoelectromechanical [9] switches with the mechanical operation of the channel, phase FET [10,11], and tunnel FETs [12,13].…”

Section: Introductionmentioning

confidence: 99%

Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator

Horri

2023

IET Circuits, Devices & Systems

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A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher I ON / I OFF ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 1010 for I ON / I OFF ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.

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Electrical Characterization of highly stable 10nm triple-gate FinFET for different contacts and oxide region materials

Cited by 6 publications

References 27 publications

Curvelet Transform Based Compression Algorithm for Low Resource Hyperspectral Image Sensors

Curvelet Transform Based Compression Algorithm for Low Resource Hyperspectral Image Sensors

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator

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