Efficient dynamic scheduling through tag elimination

Ernst, Daniel; Austin, Todd

doi:10.1145/545214.545221

Cited by 51 publications

(49 citation statements)

References 22 publications

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“…Compared to other multi-block queue designs it does not require prediction or monitoring. For example, multi-queue design of [9] requires management of multiple queues and a predictor for the last operand. The pointer-based designs are usually more complex.…”

Section: Discussionmentioning

confidence: 99%

A Simple Low-Energy Instruction Wakeup Mechanism

García-Ramírez

Cristal²,

Veidenbaum

et al. 2003

Lecture Notes in Computer Science

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Abstract. Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hardware complexity to reduce energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a mechanism for instruction wakeup, which uses a multi-block instruction queue design. The blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks.

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Section: Discussionmentioning

confidence: 99%

A Simple Low-Energy Instruction Wakeup Mechanism

García-Ramírez

Cristal²,

Veidenbaum

et al. 2003

Lecture Notes in Computer Science

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“…Ernst and Austin propose three issue queues: one without CAM logic for instructions ready at dispatch, one with CAM logic for instructions with only one nonready operand at dispatch, and a third with CAM logic for instructions with both operands nonready at dispatch. 15 …”

Section: Static Approachesmentioning

confidence: 99%

Power- and complexity-aware issue queue designs

2003

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50Current microprocessors are designed to execute instructions in parallel and out of order. In general, superscalar processors fetch instructions in order. After the branch prediction logic determines whether a branch is taken (or not) and its target address, the processor decodes the instructions and renames the register operands, removing name dependences introduced by the compiler. Because processors generally have more physical than logical registers, multiple instructions with the same logical destination can be in flight simultaneously. The renamed instructions then go into the issue queue where they wait until their operands are ready and their required resources are available. At the same time, instructions go into the reorder buffer, where they remain until they commit their results. When an instruction executes, the wakeup logic notifies dependent instructions that the corresponding operand is available. Finally, instructions commit their results in program order.This article focuses on the design of the logic that stores the instructions waiting for execution, as well as the logic associated with identifying whether operands are ready and selecting the instructions that start execution every cycle. All these components are part of the issue logic. Issue logic is one of the most complex parts of superscalar processors, one of the largest consumers of energy, and one of the main sites of power density. Its design is therefore critical for performance.Researchers have used a variety of schemes to implement the issue queue. In particular, several recent proposals have attempted to reduce the issue logic's complexity and power. To the best of our knowledge, this article is the first attempt to perform a comprehensive and thorough survey of the issue logic design space. Basic CAM-based approachesOne of the most common ways to implement the issue logic is based on contentaddressable memory (CAM) and RAM array structures. These structures can store several instructions, but generally fewer than the total number of in-flight instructions. Each entry contains an instruction that has not been issued or has been issued speculatively but not yet validated and thus might need to be reexecuted.In general, entries use RAM cells to store operations, destination operands, and flags indicating whether source operands are ready while CAM cells store source operand identifiers-referred to here as tags. Overall, the issue logic's main source of complexity and power dissipation is the many tag comparisons it must perform every cycle. Researchers have proposed several approaches to improve the issue logic's power efficiency. We classify these approaches into two groups:• static approaches, which use fixed structures, and • dynamic approaches, which dynamically adapt some structures according to the properties of the executed code.Orthogonally, researchers have proposed several more efficient circuit designs, but they don't reduce the inherent complexity. Dynamic approachesOne approach to reducing the power dissipation is b...

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“…The experiments in [6] indicate that in 80% ~ 90% of the cases one of the operands for an instruction is ready when it enters the instruction queue after renaming. However, most of them cannot be issued because the other operand is not ready and thus they wait in the instruction queue for this second operand to become available.…”

Section: Operand Pre-fetching 31 the Operand Pre-fetch Buffermentioning

confidence: 99%

The microarchitecture of a low power register file

Kim¹,

Mudge²

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

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The access time, energy and area of the register file are often critical to overall performance in wide-issue microprocessors, because these terms grow superlinearly with the number of read and write ports that are required to support wide-issue. This paper presents two techniques to reduce the number of ports of a register file intended for a wide-issue microprocessor without hardly any impact on IPC. Our results show that it is possible to replace a register file with 16 read and 8 write ports, intended for an eightissue processor, with a register file with just 8 read and 8 write ports so that the impact on IPC is a few percent. This is accomplished with the addition of several small auxiliary memory structures -a "delayed write-back queue" and a "operand prefetch buffer." We examine several configurations employing these structures separately and in combination. In the case of just the delayed write-back queue, we show an energy per access savings of about 40% and an area savings of 40%. This incurs a performance loss of just 4%. The area savings in turn has the potential for further savings by shortening global interconnect in the layout. We also show that the performance loss can be almost eliminated if both techniques are used in combination, although some area and power savings is lost.

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Efficient dynamic scheduling through tag elimination

Cited by 51 publications

References 22 publications

A Simple Low-Energy Instruction Wakeup Mechanism

A Simple Low-Energy Instruction Wakeup Mechanism

Power- and complexity-aware issue queue designs

The microarchitecture of a low power register file

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