Effect of LDD structure and channel poly-Si thinning on a gate-all-around TFT (GAT) for SRAM's

Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

“…A leakage current is increased with the increase of gate and drain voltage due to the field emission via defect-induced trap states in the depletion region near the drain. This is one of the bias-dependent issues caused by defects in poly-Si TFT devices, which cause poor switching characteristics such as low on/off current ratio [3][4][5][6][7]. It has been reported that various drain structures can decrease the leakage current in poly-Si TFTs due to reduction of electric field intensity near the drain region [8][9][10][11][12][13].…”

Superior Reliability of Gate-All-Around Polycrystalline Silicon Thin-Film Transistors with Vacuum Cavities Next to Gate Oxide Edges

“…Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted a growing amount of attention for their applications in active matrix flat-panel displays (AMFPDs), memory devices, and three-dimensional (3D) ICs. [1][2][3] In particular, owing to the feasibility of integrating peripheral driving circuits and internal pixel-switching elements, the system-on-panel (SOP) concept is expected to be realized by further increasing the performance and scaling down the feature sizes of poly-Si TFTs. 4) However, the defect states in the grain boundaries and intra-grains of poly-Si channels greatly affect the electrical characteristics and stability of poly-Si TFTs.…”

Improvements of Performance and Stability for Gate-All-Around Poly-Si TFTs Using Vacuum Cavity Structures

“…Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much attention for their applications in the active matrix flat-panel display (AMFPD), memory devices, and 3D ICs [1][2]. To further enhance the performance of driving circuits, it is necessary to scale down the feature size of TFTs to carry out the greater performance and higher packing density.…”