ECOS: Stable Matching Based Metal-Only ECO Synthesis

Jiang

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2012

Self Cite

Due to the rapidly increasing design complexity in modern integrated circuit design, more and more timing failures are detected at late stages. Without deferring time-to-market, metal-only engineering change order (ECO) is an economical technique to correct these late-found failures. Typically, a design might need to undergo many ECO runs in design houses; consequently, the usage of spare cells for ECO is of significant importance. In this paper, we aim at timing ECO by using as few spare cells as possible. We observe that a path with good timing is desired to be geometrically smooth. Unlike negative slack and gate delay used in most prior work, we propose a new metric of timing criticality, fixability, by considering the smoothness of timing violating paths. To measure the smoothness of a path, we use the Bézier curve as the golden path. Furthermore, in order to concurrently fix timing violations, we derive a propagation property to divide violating paths into independent segments. Based on Bézier curve smoothing, fixability identification, and the propagation property, we develop an efficient algorithm to fix timing violations. Experimental results show that we can effectively resolve all timing violations with significant speedups over the state-of-the-art works.

Section: A Prior Workmentioning

confidence: 99%

Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification

Jiang

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2012

Self Cite

“…These incremental changes can be functional ECO, dedicated for functional rectification or specification modification, or timing ECO, dedicated for timing closure and optimization. Recently, metal-only ECO has drawn great attentions in literature, e.g., [2,3,4,5,6,7,8,9,10,11,12,13]. To enable metal-only ECO, (redundant) spare cells are inserted at the early placement and routing stage.…”

Section: Introductionmentioning

confidence: 99%

“…To enable metal-only ECO, (redundant) spare cells are inserted at the early placement and routing stage. Most of prior works regard standard cells as spare cells, e.g., [2,3,4,5,6,7,8,9,10,11]. Nevertheless, these pre-inserted standard spare cells are limited by their pre-determined quantity, functionality, and locations.…”

Section: Introductionmentioning

confidence: 99%

“…A standard spare cell has one designated functionality, while a spare array may serve various functionalities or form different combinations of functional cells. Unlike the conventional functional ECO problem, which incurs the dynamic physical cost issue [9], the new functional ECO problem possesses the dynamic logical and physical cost nature. By dynamic physical cost, we mean that the internal wiring among standard spare cells changes dynamically during standard spare cell selection.…”

Section: Introductionmentioning

confidence: 99%

“…State-of-the-art functional ECO frameworks, e.g., [9,10,11], usually include two major steps: First, they convert an ECO patch, which defines the logic difference between the original and revised designs, to available spare cell types. Initially, they presume spare cells for each type to be sufficient.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Functional ECO Using Metal-Configurable Gate-Array Spare Cells

Jiang

Proceedings of the 51st Annual Design Automation Conference

2014

Self Cite

Metal-configurable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional ECO problem has the nature of dynamic logical and physical costs for selecting spare gate arrays. Unlike existing functional ECO works, which perform technology mapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and map between the logical ECO network and the physical spare array relation graph.

IET Circuits, Devices & Systems

Unified approach for simultaneous functional and timing ECO

Hung

Lin

Cheng

et al. 2016

Engineering change order (ECO) is a technique commonly used in the later integrated circuit design stages to reduce redesign efforts and time-to-market. ECO problems are generally categorised according to functional changes (functional ECO) or timing violations (timing ECO). This study differs from conventional approaches in its adoption of a solution that involves unifying functional ECO with timing ECO. The authors applied the concept of virtual nodes to the problem of transforming timing ECO into functional ECO. In addition to buffer insertion and gate sizing, the authors developed a novel detour reduction method for the repair of timing violation paths. Technology mapping is used to facilitate the selection of spare cells, through the generation of various revisions for each ECO. The unified ECO problem is then solved using a novel modification of the Hungarian matching algorithm. Experiment result demonstrates the efficacy of the proposed approach at solving both types of ECO simultaneously.