Dynamic memory disambiguation in the presence of out-of-order store issuing

Önder, Soner; Gupta, Rajiv

doi:10.1109/micro.1999.809454

Cited by 14 publications

(15 citation statements)

References 8 publications

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“…We choose this scheme as one of the bases for our evaluation and describe the algorithm and implementation in detail in Section 2.3.1. Yoaz et al [26] present a dynamic store distance based technique that uses less space than store set, but does not perform as well.Önder and Gupta [19] have shown that the restriction of issuing store instructions in-order can be removed and store instructions can be allowed to execute out-of-order if the memory order violation detection mechanism is modified appropriately. Furthermore, they have shown that memory order violation detection can be based on values, instead of addresses.Önder [17] has proposed a light-weight memory dependence predictor which uses multiple speculation levels in the hardware to direct load speculation.…”

Section: Memory Disambiguationmentioning

confidence: 99%

“…In this work, we use a mis-speculation handling mechanism very similar to that proposed byÖnder and Gupta [19]. Detection of the memory order violations is performed by recording the load instruction's effective address, the load's ID and the producer store's ID in a table called the speculative load table when a load instruction is issued speculatively.…”

Section: Figure 4: Store Table Implementationmentioning

confidence: 99%

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Feedback-directed memory disambiguation through store distance analysis

Fang¹,

Carr

Önder

et al. 2006

Proceedings of the 20th Annual International Conference on Supercomputing

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Feedback-directed optimization has developed into an increasingly important tool in designing optimizing compilers. Based upon profiling, memory distance analysis has shown much promise in predicting data locality and memory dependences, and has seen use in locality based optimizations and memory disambiguation. In this paper, we apply a form of memory distance, called store distance, to the problem of memory disambiguation in out-of-order issue processors. Store distance is defined as the number of store references between a load and the previous store accessing the same memory location. By generating a representative store distance for each load instruction, we can apply a compiler/micro-architecture cooperative scheme to direct run-time load speculation. Using store distance, the processor can, in most cases, accurately determine on which specific store instruction a load depends according to its store distance annotation. Our experiments show that the proposed store distance method performs much better than the previous distance based memory disambiguation scheme, and yields a performance very close to perfect memory disambiguation. The store distance based scheme also outperforms the store set technique with a relatively small predictor space and achieves performance comparable to that of a 16K-entry store set implementation for both floating point and integer programs.

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Section: Memory Disambiguationmentioning

confidence: 99%

Section: Figure 4: Store Table Implementationmentioning

confidence: 99%

Feedback-directed memory disambiguation through store distance analysis

Fang¹,

Carr

Önder

et al. 2006

Proceedings of the 20th Annual International Conference on Supercomputing

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“…Both load and store instructions are allowed to issue out-of-order [6,17] using the store set memory dependence predictor. Five models with different misprediction recovery mechanisms are evaluated and compared:…”

Section: Figure 10: Machine Modelmentioning

confidence: 99%

Fast branch misprediction recovery in out-of-order superscalar processors

Zhou

Önder

Carr

2005

Proceedings of the 19th Annual International Conference on Supercomputing

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Current trends in modern out-of-order processors involve implementing deeper pipelines and a large instruction window to achieve high performance. However, as pipeline depth increases, the branch misprediction penalty becomes a critical factor in overall processor performance. Current approaches to handling branch mispredictions either incrementally roll back to in-order state by waiting until the mispredicted branch reaches the head of the reorder buffer, or utilize checkpointing at branches for faster recovery. Rolling back to in-order state stalls the pipeline for a significant number of cycles and checkpointing is costly.This paper proposes a fast recovery mechanism, called Eager Misprediction Recovery (EMR), to reduce the branch misprediction penalty. Upon a misprediction, the processor immediately starts fetching and renaming instructions from the correct path without restoring the map table. Those instructions that access incorrect speculative values wait until the correct data are restored; however, instructions that access correct values continue executing while recovery occurs. Thus, the recovery mechanism hides the latency of long branch recovery with useful instructions.EMR achieves a mean performance improvement very close to a recovery mechanism that supports checkpointing at each branch. In addition, EMR provides an average of 9.0% and up to 19.9% better performance than traditional sequential misprediction recovery on the SPEC2000 benchmark suite.

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“…Onder and Gupta [17] have shown that when multiple successive stores to the same address write the same value, a subsequent load to that address may be safely moved prior to all of those stores except the first as long as the memory order violation detection hardware examines the values of loads and stores. Given the following sequence of memory operations,…”

Section: Value Distance and Speculationmentioning

confidence: 99%

“…Onder and Gupta [17] have shown that the restriction of issuing store instructions in-order can be removed and store instructions can be allowed to execute out-of-order if the memory order violation detection mechanism is modified appropriately. Furthermore, they have shown that memory order violation detection can be based on values, instead of addresses.…”

Section: Related Workmentioning

confidence: 99%