Dynamic management of scratch-pad memory space

Kandemir, M.; Ramanujam, J.; Irwin, M.J.; Vijaykrishnan, N.; Kadayif, I.; Parikh, A.

doi:10.1109/dac.2001.935595

Cited by 92 publications

(180 citation statements)

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“…We are interested in data management [18,22,23], and target dynamic methods which are superior to static ones except when code size is extremely constrained [16]. We elaborate on two recent series of results targeting stack and global array management in LMs, embracing the analogies with register allocation.…”

Section: Related Workmentioning

confidence: 99%

“…We currently restrict our approach to uniform array accesses only. Non-uniform accesses can be exploited through approximations or pre-pass loop and data-layout transformations [18,25,26]. We consider loop nests that have been previously tiled for locality, together with data layout compaction and uniformization.…”

Section: Preliminary Analyses and Transformationsmentioning

confidence: 99%

“…When generating the code for a real target, one needs to insert code for array block load/store, and pointer moves. Again, standard techniques exist when array accesses are uniform [17,18].…”

Section: Preliminary Analyses and Transformationsmentioning

confidence: 99%

“…Some heuristics exist [16,17,18,19] but little is known about the optimization problem, its complexity and the interplay with other optimizations. The burning hot question is of course: does the decoupled approach hold for the LM management problem?…”

Section: Motivationmentioning

confidence: 99%

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Optimizing Local Memory Allocation and Assignment through a Decoupled Approach

Diouf

Öztürk

Cohen

2010

Languages and Compilers for Parallel Computing

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Abstract. Software-controlled local memories (LMs) are widely used to provide fast, scalable, power efficient and predictable access to critical data. While many studies addressed LM management, keeping hot data in the LM continues to cause major headache. This paper revisits LM management of arrays in light of recent progresses in register allocation, supporting multiple live-range splitting schemes through a generic integer linear program. These schemes differ in the grain of decision points. The model can also be extended to address fragmentation, assigning live ranges to precise offsets. We show that the links between LM management and register allocation have been underexploited, leaving much fundamental questions open and effective applications to be explored.

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Section: Related Workmentioning

confidence: 99%

Section: Preliminary Analyses and Transformationsmentioning

confidence: 99%

Section: Preliminary Analyses and Transformationsmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%

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Optimizing Local Memory Allocation and Assignment through a Decoupled Approach

Diouf

Öztürk

Cohen

2010

Languages and Compilers for Parallel Computing

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“…After trying all functions, we update the current mapping by moving function bf to region br (line [21][22]. br being greater than nr means that we just made a new region, so we increase the number of regions (line [23][24]. We stop when the cost of the mapping does not get improved.…”

mentioning

confidence: 99%

WCET-aware dynamic code management on scratchpads for Software-Managed Multicores

Kim

Broman

Cai

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Abstract-Software Managed Multicore (SMM) architectures have advantageous scalability, power efficiency, and predictability characteristics, making SMM particularly promising for real-time systems. In SMM architectures, each core can only access its scratchpad memory (SPM); any access to main memory is done explicitly by DMA instructions. As a consequence, dynamic code management techniques are essential for loading program code from the main memory to SPM. Current state-of-the-art dynamic code management techniques for SMM architectures are, however, optimized for average-case execution time, not worst-case execution time (WCET), which is vital for hard real-time systems. In this paper, we present two novel WCET-aware dynamic SPM code management techniques for SMM architectures. The first technique is optimal and based on integer linear programming (ILP), whereas the second technique is a heuristic that is suboptimal, but scalable. Experimental results with benchmarks from Mälardalen WCET suite and MiBench suite show that our ILP solution can reduce the WCET estimates up to 80% compared to previous techniques. Furthermore, our heuristic can, for most benchmarks, find the same optimal mappings within one second on a 2GHz dual core machine.

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Programming multi‐core and many‐core computing systems

Pllana¹,

Xhafa²

2017

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As applications become more and more complex, it is becoming extremely important to have sufficient compute power on the chip. Multicore and manycore systems have been introduced to address this problem. While multicore system performance and power consumption are greatly affected by application data access characteristics, the compiler optimizations can make a significant difference. Considering that cost of off-chip memory accesses is continuously rising in terms of CPU cycles, it is critical to cut down the number of off-chip memory accesses.Accessing off-chip memory presents at least three major problems in a multicore architecture. First, off-chip memory latencies are continuously increasing due to increases in processor clock frequencies. Consequently, large performance penalties are paid even if a small fraction of memory references go off chip. Second, the bandwidth between the multicore processor and the off-chip memory may not be sufficient to handle simultaneous off-chip access requests coming from multiple processors.

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Dynamic management of scratch-pad memory space

Cited by 92 publications

References 0 publications

Optimizing Local Memory Allocation and Assignment through a Decoupled Approach

Optimizing Local Memory Allocation and Assignment through a Decoupled Approach

WCET-aware dynamic code management on scratchpads for Software-Managed Multicores

Programming multi‐core and many‐core computing systems

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