DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations

Salehi, M T Zahraei; Tavana, Mohammad Khavari; Rehman, Semeen; Kriebel, Florian; Shafique, Muhammad; Ejlali, Alireza; Henkel, Jörg

doi:10.1109/islped.2015.7273518

Cited by 45 publications

(23 citation statements)

References 24 publications

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“…Haque et al used replication to attain reliability while saving energy with DVS [24] and presented the interplay of energy, reliability, frequency, and replication. Similar work has been done for dependent tasks by Salehi et al [25] for three-level of redundancy that includes single execution (SE), dual modular redundancy (DMR) and triple modular redundancy (TMR).…”

Section: Related Workmentioning

confidence: 82%

Fault-Tolerant Energy-Aware Task Scheduling on Multiprocessor System for Fixed-Priority Real-Time Tasks

Arora*,

Bansal,

Bansal

2019

IJITEE

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Energy-aware real-time scheduling is gaining attention in recent years owing to environmental concerns and applications in numerous fields. System reliability also gets affected adversely with increasing energy dissipations posing serious challenges before the researchers. Keeping these in view, in recent times researchers have diverted to combining issues of fault-tolerance and energy efficiency. In literature, DVFS and DPM, most commonly used techniques for power management in task scheduling, are often combined with Primary/Backup technique to achieve fault tolerance against transient and permanent faults. Optimal algorithms, Earliest deadline first (EDF) and Rate-Monotonic (RM), meant for scheduling dynamic and fixed priority tasks respectively, have mainly been analyzed using a dual-processor approach for fault-tolerance and energy efficiency. In this paper, to handle higher workload of fixed-priority real-time tasks, energy-aware fault-tolerant scheduling algorithms are proposed for multiprocessor systems with balanced and unbalanced number of main and auxiliary processors. Simulations over extensive task-sets indicate that balanced approach is more energy-efficient than the unbalanced one.

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Section: Related Workmentioning

confidence: 82%

Fault-Tolerant Energy-Aware Task Scheduling on Multiprocessor System for Fixed-Priority Real-Time Tasks

Arora*,

Bansal,

Bansal

2019

IJITEE

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“…These reliable applications or respective thread can jointly be used with hardware techniques to improve the overall reliability of the multi/many-core heterogeneous processor. Another solution is to exploit the dynamic voltage and frequency scaling to generate the dynamic redundancy and voltage scaling with respect to the effects of process variations, application vulnerability, performance overhead, and design constraints [40]. This technique demonstrates up to 60% power reductions while improving the reliability significantly.…”

Section: Variability-aware Reliability-heterogeneous Processor [21]: mentioning

confidence: 99%

Fault-Tolerant Computing with Heterogeneous Hardening Modes

Kriebel

Khalid

Prabakaran

et al. 2020

Dependable Embedded Systems

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Fault-tolerance using (full-scale) redundancy-based techniques has been employed to detect and correct reliability errors (i.e., soft errors), but they pose significant area and power overhead. On the other hand, due to the masking and the error tolerance properties at different system layers and of different applications, respectively, reliable heterogeneous architectures have been emerged as an attractive design choice for power-efficient dependable computing platforms. This chapter discusses the building blocks of such computing systems, based on both embedded and superscalar processors, with different reliability (fault-tolerant) modes at the architecture layer to memories like caches, for heterogeneous in-order and out-of-order processors. We provide a comprehensive reliability, i.e., soft error, vulnerability analysis of different components in in-order and out-of-order processors, e.g., caches. We also discuss different methodologies to improve the performance and power of such a system by analyzing these vulnerabilities. Moreover, we show how such heterogeneous hardware-level hardening modes can further be complemented by software-level techniques that can be realized using a reliability-driven compiler (as introduced in Chapter “Dependable Software Generation and Execution on Embedded Systems”).

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“…The static power P Static increases exponentially when the threshold voltage (V th ) decreases and is proportional to the supply voltage (V ). The dynamic power P Dynamic is proportional to the circuit switching activity (α), load capacitance (C L ), operating frequency (f ), and the square of the supply voltage (V ) [11,12,14,15].…”

Section: Power Consumption Modelmentioning

confidence: 99%

Power-Aware Fault-Tolerance for Embedded Systems

Salehi

Kriebel

Rehman

et al. 2020

Dependable Embedded Systems

Self Cite

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Power-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be “dark.” In this chapter, a system-level power–reliability management technique is presented. The technique jointly considers multiple hardening modes at the software and hardware levels, each offering distinct power, reliability, and performance properties. Also, a framework for the system-level optimization is introduced which considers different power–reliability–performance management problems for many-core processors depending upon the target system and user constraints.

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DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations

Cited by 45 publications

References 24 publications

Fault-Tolerant Energy-Aware Task Scheduling on Multiprocessor System for Fixed-Priority Real-Time Tasks

Fault-Tolerant Energy-Aware Task Scheduling on Multiprocessor System for Fixed-Priority Real-Time Tasks

Fault-Tolerant Computing with Heterogeneous Hardening Modes

Power-Aware Fault-Tolerance for Embedded Systems

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