Driving Current Enhancement of Strained Ge (110) p-Type Tunnel FETs and Anisotropic Effect

Abstract

The experimental investigation carried out the strained Ge (110) p-type tunneling field-effect transistor, and it resulted in the current enhancement of x2.9 BTBT in the < 112 > direction, as compared with Si < 110 > / (100) due to a small band gap. In addition, the high ON/OFF current ratio, with an ON current similar to 1 mu A/mu m and an OFF current similar to 10 pA/mu m, and the well control for leakage current without SOI substrate were obtained. The anisotropic effect of tunneling directions for strained Ge on (110) orientation was discussed and explained as due to effective reduced mass

Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio

“…Therefore, we believe that the characteristics of the Ge ETL TFET could be further improved by optimizing the thickness of the Ge ETL. Table I summarizes the performance of current state-of-the-art Ge-based planar p-TFETs [11][12][13][14][15]. All the TFETs are compared with the OFF-state current (V G = 0V) targeted to 10 pA/μm through the adjustment of V TH .…”

Relaxed germanium-tin P-channel tunneling field-effect transistors fabricated on Si: impacts of Sn composition and uniaxial tensile strain

“…Current pTFETs mainly employed group IV materials, such as SiGe, Ge, and GeSn. [18][19][20][21] Recently, a great progress of relative theory and experiments in developing GeSn channel TFETs has been done, which attracted much attention. [21][22][23][24][25][26][27] By tuning Sn composition and applying proper strain, GeSn can be a semiconductor with small and direct E G , thereby exhibiting a high BTBT rate in TFETs.…”

Current Enhancement of Green Transistors Compared with Conventional Tunnel Field-Effect Transistors

“…Besides, there are many studies on the modeling and simulation of TFETs including those of Si-based and III-V TFETs. [15][16][17][18][19][20][21][22][23][24][25] Recently, epi-Ge p-TFETs 26) on bulk (110) substrates and planar p-type gFETs (p-gFETs) on SOI 9) have been reported with high I on values of 1 and 1.2 A/m, respectively. For these FETs to be compatible with current processes, in this study, we fabricated a p-type TFET and a p-type gFET (p-gFET) with Ni dopant segregation 9,27) at the source and drain region on bulk Si(100) without the SOI substrate, and an integrated high-K metal gate (HKMG) stack.…”

“…For these FETs to be compatible with current processes, in this study, we fabricated a p-type TFET and a p-type gFET (p-gFET) with Ni dopant segregation 9,27) at the source and drain region on bulk Si(100) without the SOI substrate, and an integrated high-K metal gate (HKMG) stack. 26)…”