DRAM energy management using software and hardware directed power mode control

Symbolic expression analysis for compiled communication

“…This locality is due to loop structures in the code and leads to the subdivision of the application into computational phases typically based on loop structures [3]. Much like the computational phases within the application, for parallel applications, there exists a similar locality of communication.…”

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling

“…Early works on reducing DRAM background power propose hardware and software policies for switching to low power DRAM modes [3][4][5][6], [18]. Our techniques further reduce DRAM background by servicing most of the required refreshes in the lowest power mode.…”

“…A simple history-based prediction (HBP) has been proposed by Delaluz et al [3] to predict the next inter-access time based on the previous inter-access time value. We observe that HBP's approach of relying only on one previous idle period length makes it incapable of capturing common patterns present in many programs, like alternating low and high activity phases.…”

“…For example, in the deepest low power Self Refresh (SR) mode, the entire clocked DRAM circuitry is turned off, resulting in no additional power dissipation beyond the power required to refresh the DRAM cells. Many previous papers have proposed intelligent schemes to utilize these low power modes to save DRAM power [3][4][5][6][7][8]. The key idea behind these schemes is to switch a DRAM rank to a lower power mode whenever the rank stays idle for a time period longer than a pre-determined threshold.…”

“…To that end, we add two more optimization techniques. First, we augment the history based prediction scheme proposed in [3], which tracks the length of previous idle periods to accurately predict the length of current idle period. We use this prediction to guide the thresholds for switching to low power modes in our coordinated refresh techniques.…”