Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

Shaikh, Mohd Rizwan Uddin; Loan, Sajad A.

doi:10.1109/ted.2019.2896674

Cited by 82 publications

(19 citation statements)

References 30 publications

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“…The process starts with a 10 nm thick, lightly doped silicon wafer with doping N C ≈ 1×10 17 atoms/cm 3 , as shown in Fig 2(a). Then, using atomic layer deposition (ALD) technique, a 2 nm thick Hf O 2 layer is deposited on the silicon surface, as shown in Fig 2(b) [31]- [33]. This is followed by the deposition of a 3 nm thick metal layer (M 1 ) with a work-function φ 1 , using the e-beam deposition technique, as shown in Fig.…”

Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this paper, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFFstate current (ION /IOF F) ratio of order ∼ 10 9. Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

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Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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“…A tunnelling field‐effect transistor (TFET) has become a kind of promising candidate for the ultra‐low power consumption applications in the nanoscale circuit because of overcoming a limitation of 60 mV/Dec subthreshold swing (SS) [1–8]. However, band‐to‐band tunnelling (BTBT) is the main working mechanism in TFETS [9–16], which leads to an inherent disadvantage in terms of ON‐state current [17–28].…”

Section: Introductionmentioning

confidence: 99%

TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel

Xie

Liu

Han

et al. 2020

Micro & Nano Letters

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In this work, the authors propose and simulate a double L-shaped gate tunnel field-effect transistor (DLG-TFET) with the covered source-channel. The proposed structure improves the ON-state current by increasing the linear tunnelling area and has excellent subthreshold characteristics. The simulation focuses on the performance improvement of the device under different longitudinal gate length L g , interlayer silicon thickness T si , gate and source overlap length L ov , and covered source depth L s. For optimal parameters, the ON-state current of the proposed DLG-TFET increases up to 3.53 × 10 −5 A/μm, and the current switch ratio(I on /I off) is 4.28 × 10 11 at room temperature, moreover, a minimum subthreshold swing (SSmin) and an average subthreshold swing (SSave) are as low as 32.2 and 52.9 mV/Dec, respectively. Meanwhile, this work uses mixed device-circuit simulations to predict the performance of the inverter circuit implemented with proposed DLG-TFET.

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“…The ambipolar current may become further increase with down scaling of device dimension and with the use of low bandgap materials. Various approaches have been proposed for reducing the ambipolarity 23‐30 . However, they result in ON current degradation, increased complexity poor frequency response.…”

Section: Introductionmentioning

confidence: 99%

“…The use of dual material gate 27 has increased the total gate capacitance and hence degraded the overall performance. The use of Gaussian drain doping, 26,29 multiple work function, 31,32 and multiple equivalent oxide thickness (EOT)'s 28 for drain and separate EOT for gate for doping‐less architecture also exhibits the structural complexity, and it is prone to the process variation. The gate‐drain underlap and overlap approaches have been very popular and fabrication friendly.…”

Section: Introductionmentioning

confidence: 99%

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Haris

Loan

Mainuddin

2020

Int J Numerical Modelling

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In this work, we present the design and simulation of a novel structure of In0.53Ga0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main gate at an optimized separation from gate electrode. The PSG is not an active gate and it is not connected to either VDD or gate voltage. Two dimensional simulation study has revealed that the proposed device suppresses ambipolar current by ~10 orders of magnitude as compared to a HTFET without overlap and by >7 orders as compared to overlapping gate on drain HTFET (OGD‐HTFET). The PSG‐based HTFET (PSG‐HTFET) also exhibits lesser total gate capacitance as compared to OGD TFET. The proposed PSG‐HTFET offers much better ambipolar suppression even at higher drain doping and lower EOT, as compared to OGD‐HTFET. Further, the PSG‐HTFET exhibits 50% and 40% lesser fall and rise propagation delays respectively as compared to the OGD‐HTEFT. Further, the voltage overshoot and undershoot have also been suppressed in the proposed PSG‐HTFET. The scalability analysis shows that the PSG‐HTFET has better scalability in terms of ambipolar suppression, total gate capacitance, and propagation delays.

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Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

Cited by 82 publications

References 30 publications

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

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Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

Cited by 82 publications

References 30 publications

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel

Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

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Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis